US3928857A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Instruction fetch apparatus with combined look-ahead and look-behind capability
Assignee: International Business Machines Corp
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Filing: 1973-08-30
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Granted: 1975-12-23
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Expires: 1993-08-30
Abstract
Abstract Apparatus for fetching instructions to an instruction register of a central processing unit, including instruction buffers for storing instructions prior to their execution in the CPU (lookahead) and apparatus for storing instructions which have been executed in the CPU (look-behind) in anticipation of their further use in, for example, programming loops. The look-behind apparatus comprises a multi-word buffer with its associated data register. The buffer data register, in addition to its function as part of the look-behind apparatus, also provides an additional level of look-ahead.
Inventors
- 👤 Richard S Carter
- 👤 Jr Spurgeon G Hogan
- 👤 Wan L Leung
- 👤 Bruce L Mcgilvray
- 👤 Robert H Werner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:02
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3808; G06F9/381
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
364 words
In a data processing system which includes a system storage, a processing unit, addressing means for addressing a location in said system storage which contains a desired instruction; improved means for transferring said desired instruction to said processing unit comprising: instruction buffering means (I-buffer) comprising an auxiliary multi-word memory for storing only a plurality of instructions; means interconnecting said system storage to said I-buffer for transmission of instructions from said system storage to said I-buffer; means interconnecting said I-buffer to said processing unit for transmission of instructions from said I-buffer to said processing unit; means interconnecting said addressing means to said I-buffer for addressing a specific location within said I-buffer that is at least partially defined by an address in said adressing means; I-buffer indexing means (IBIX) comprising a multi-word memory for storing at least portions of each of a plurality of the system storage addresses of instructions contained in said Ibuffer; means interconnecting said addressing means to said IBIX for addressing a location within said IBIX that corresponds to said specific location within said I-buffer; comparison means; means interconnecting said IBIX to an input of said comparison means and means interconnecting said addressing means to another input of said comparison means for comparing address information read from said IBIX to address information contained in said addressing means; said comparison means, upon detection of equality at said two inputs, causing generation of a data available signal which indicates that a desired instruction is contained within said I-buffer; means within said system responsive to said data available signal to fetch said desired instruction to said processing unit from said I-buffer instead of from said system storage; means responsive, after a comparison by said comparison means, to the absence of said data available signal to cause said desired instruction to be fetched from said system storage; means responsive to said absence of said data available signal after said comparison for also causing said desired instruction to be stored into said I-buffer; and means responsive to said absence of said data available signal after said comparison for causing at least a portion of the system storage address of said desired instruction to be stored into said IBIX.
Claim 2
Dependent Claim
364 words
In a data processing system which includes a system storage, a processing unit, addressing means for addressing a location in said system storage which contains a desired instruction; improved means for transferring said desired instruction to said processing unit comprising: instruction buffering means (I-buffer) comprising an auxiliary multi-word memory for storing only a plurality of instructions; means interconnecting said system storage to said I-buffer for transmission of instructions from said system storage to said I-buffer; means interconnecting said I-buffer to said processing unit for transmission of instructions from said I-buffer to said processing unit; means interconnecting said addressing means to said I-buffer for addressing a specific location within said I-buffer that is at least partially defined by an address in said adressing means; I-buffer indexing means (IBIX) comprising a multi-word memory for storing at least portions of each of a plurality of the system storage addresses of instructions contained in said Ibuffer; means interconnecting said addressing means to said IBIX for addressing a location within said IBIX that corresponds to said specific location within said I-buffer; comparison means; means interconnecting said IBIX to an input of said comparison means and means interconnecting said addressing means to another input of said comparison means for comparing address information read from said IBIX to address information contained in said addressing means; said comparison means, upon detection of equality at said two inputs, causing generation of a data available signal which indicates that a desired instruction is contained within said I-buffer; means within said system responsive to said data available signal to fetch said desired instruction to said processing unit from said I-buffer instead of from said system storage; means responsive, after a comparison by said comparison means, to the absence of said data available signal to cause said desired instruction to be fetched from said system storage; means responsive to said absence of said data available signal after said comparison for also causing said desired instruction to be stored into said I-buffer; and means responsive to said absence of said data available signal after said comparison for causing at least a portion of the system storage address of said desired instruction to be stored into said IBIX.
Claim 3
Dependent Claim
51 words
The improved apparatus of claim 1 wherein: said I-buffer is of sufficient capacity to store n instructions; and said IBIX is of sufficient capacity to store n/m portions of addresses; each portion of a system storage address stored in said IBIX being logically associated with m instruction addresses of said I-buffer.
Claim 4
Dependent Claim
10 words
The improved apparatus of claim 2 wherein m equals 2.
Claim 5
Dependent Claim
81 words
The improved apparatus of claim 2 wherein: there is stored in said IBIX, along with each portion of a system storage address, one or more selectively settable validity indicators for identifying the one or ones of the m logically associated I-buffer addresses for which the entry in the IBIX is currently valid; and wherein said improved apparatus additionally comprises means responsive to said validity indicators for allowing generation of said data available signal only when an appropriate validity indicator is set.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-12-22 | 1979-06-23 | 1979-12-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-12-22 | 1983-06-23 | 1983-12-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-12-22 | 1987-06-23 | 1987-12-23 | $7700.00 | Window Closed / Lapsed |