US4528640A
Expired / Lapsed
US
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Method and a means for checking normalizing operations in a computer device
Assignee: Unisys Corp
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Filing: 1982-07-13
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Granted: 1985-07-09
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Expires: 2002-07-13
Abstract
Abstract A method and a means are disclosed for the throughchecking of the normalizer operations of an arithmetic unit of a data processing system involving both integer and floating-point formats in single and double precision operations. A post normalizer is used in conjunction with the main normalizer of the arithmetic unit to determine if the result is indeed normalized. Where the post normalize count is zero, an error designator remains inactivated. However, where the count is non-zero, the error designator is activated to indicate an error exists, unless it is disabled by separate circuitry which detects that the number being shifted is +/-O. The preferred embodiment disclosed herein checks the operation of a pair of 72-bit main normalizers with a single 13-bit post normalizer. A plurality of instructions in which this check is significant are illustrated.
Inventors
- 👤 Peter B. Criswell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 12:21
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0763
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
154 words
Apparatus for throughchecking the normalizing operations of a main normalizer means of an arithmetic unit means of a data processing system comprising: (a) main normalizer means included in said arithmetic unit means; (b) arithmetic unit normalized shift matrix output means associated with said arithmetic unit means and said main normalizer means for providing output signals; (c) register means coupled to said arithmetic unit normalized shift matrix output means to capture said output signals therefrom; (d) post normalizer circuit means coupled to said register means and responsive to captured ones of said output signals for identifying normalization error conditions; (e) error detector means coupled to said post normalizer circuit means for detecting error conditions; and (f) error designator circuit means having input means and output means, said input means connected to said error detector means to respond to the presence of a detected error and thereby provide a designated error signal at said output means.
Claim 2
Dependent Claim
154 words
Apparatus for throughchecking the normalizing operations of a main normalizer means of an arithmetic unit means of a data processing system comprising: (a) main normalizer means included in said arithmetic unit means; (b) arithmetic unit normalized shift matrix output means associated with said arithmetic unit means and said main normalizer means for providing output signals; (c) register means coupled to said arithmetic unit normalized shift matrix output means to capture said output signals therefrom; (d) post normalizer circuit means coupled to said register means and responsive to captured ones of said output signals for identifying normalization error conditions; (e) error detector means coupled to said post normalizer circuit means for detecting error conditions; and (f) error designator circuit means having input means and output means, said input means connected to said error detector means to respond to the presence of a detected error and thereby provide a designated error signal at said output means.
Claim 3
Dependent Claim
36 words
The apparatus for throughchecking the normalizing operation as set forth in claim 1 wherein both said post normalizer circuit means and said main normalizer means of said arithmetic unit means are of the same circuit type.
Claim 4
Dependent Claim
42 words
The apparatus for throughchecking the normalizing operation as set forth in claim 1 wherein said error designator circuit means includes a latching circuit which provides a first and a second output signal to denote an error condition and a non-error condition, respectively.
Claim 5
Dependent Claim
75 words
A normalizer throughchecking circuit comprising a post normalizer circuit connected to the main normalizer circuit of an arithmetic unit of a data processing system; shift/nonshift indicating means for indicating a shift or a non-shift condition of said post normalizer circuit connected to said post normalizer circuit; and error/non-error indicating means connected to said shift/nonshift indicating means for indicating an error signal when a shift is indicated and a non-error signal when a non-shift is indicated.
Claim 6
Dependent Claim
75 words
A normalizer throughchecking circuit comprising a post normalizer circuit connected to the main normalizer circuit of an arithmetic unit of a data processing system; shift/nonshift indicating means for indicating a shift or a non-shift condition of said post normalizer circuit connected to said post normalizer circuit; and error/non-error indicating means connected to said shift/nonshift indicating means for indicating an error signal when a shift is indicated and a non-error signal when a non-shift is indicated.
Claim 7
Dependent Claim
25 words
The normalizer throughchecking circuit of claim 4 wherein said post normalizer circuit is a second normalizer circuit corresponding in configuration to said main normalizer circuit.
Claim 8
Dependent Claim
23 words
The normalizer throughchecking circuit of claim 4 wherein said shift/nonshift indicating means for indicating a shift or non-shift condition is an OR gate.
Claim 9
Dependent Claim
35 words
The normalizer throughchecking circuit of claim 4 wherein said error/non-error indicating means includes a bistable device capable of indicating an error signal in one stable condition and a non-error signal in the opposite stable condition.
Claim 10
Dependent Claim
34 words
The normalizer throughchecking circuit of claim 7 wherein said bistable device includes a further input means for disabling/enabling said device when predetermined instructions indicate that the output of said bistable device would be erroneous.
Claim 11
Dependent Claim
15 words
The normalizer throughchecking circuit of claim 8 wherein said bistable device is a latch circuit.
Claim 12
Dependent Claim
26 words
The normalizer throughchecking circuit of claim 7 wherein said error/non-error indicating means further includes an AND gate connected as an input to said error/non-error indicating means.
Claim 13
Independent Claim
125 words
A method of throughchecking the normalizer paths of an arithmetic unit of a data processing system comprising the steps of: (a) applying the shifted output from a shift matrix to a further normalizer to check that the count and the direction supplied by main normalizer of the arithmetic unit has been accomplished, and to provide a first output; (b) applying the first output of the further normalizer to an error detecting means to provide a second output to indicate an error if the shift has not been accomplished; and (c) applying the second output of the error detecting means to an error designator means to activate said error designator means when the shift directed to be accomplished is not equal to the shift actually accomplished.
Claim 14
Independent Claim
125 words
A method of throughchecking the normalizer paths of an arithmetic unit of a data processing system comprising the steps of: (a) applying the shifted output from a shift matrix to a further normalizer to check that the count and the direction supplied by main normalizer of the arithmetic unit has been accomplished, and to provide a first output; (b) applying the first output of the further normalizer to an error detecting means to provide a second output to indicate an error if the shift has not been accomplished; and (c) applying the second output of the error detecting means to an error designator means to activate said error designator means when the shift directed to be accomplished is not equal to the shift actually accomplished.
Claim 15
Dependent Claim
49 words
The method as set forth in claim 11 including separate further circuitry means for disabling of the error detection circuitry where the separate further circuitry detects that the number being shifted is ±.0. or cannot be normalized by an instruction doing a limited shift rather than a full normalization.
Claim 16
Dependent Claim
23 words
The method as set forth in claim 12 where the instruction doing the limited shift is a floating-point multiply, divide, compression or expansion.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-07-08 | 1989-01-07 | 1989-07-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-07-08 | 1993-01-07 | 1993-07-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-07-08 | 1997-01-07 | 1997-07-09 | $7700.00 | Window Closed / Lapsed |