US4922446A
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US
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Apparatus and method for floating point normalization prediction
Assignee: Hewlett Packard Development Co LP
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Filing: 1988-04-01
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Granted: 1990-05-01
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Expires: 2008-04-01
Abstract
Abstract The invention is directed to an apparatus and method for predicting the number of bits which must be taken into account to normalize the result of a floating point addition or subtraction. The apparatus and method employ: a low precision floating point adder/subtractor, a priority encoder that determines the position of the most significant non-zero bit to generate the normalization amount and preround logic which pre-shifts a rounding bit in the opposite direction of normalization. The method and apparatus operate in parallel with a full precision floating point adder to eliminate the need for a full-precision floating point normalization calculation and rounding computation in most circumstances. The normalization amount for successful low-precision floating-point addition/subtraction is calculated by the time the full-precision floating-point addition/subtraction stage occurs. Moreover, the pre-round logic supplies a carry bit to the full-precision adder/subtractor thus saving the time associated with a full-precision rounding bit addition. Thus, this low-precision floating-point addition/subtraction technique results in a significant enhancement of performance in floating-point addition/subtraction.
Inventors
- 👤 John H. Zurawski
- 👤 Kathleen P. Harrington
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 05:27
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/483; G06F7/485; G06F5/00; G06F5/01; G06F5/012; G06F7/499; G06F7/49942; G06F7/49947
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
122 words
An arithmetic logic device, which comprises: (a) a first addition and subtraction device operating to perform a first arithmetic function on operands to obtain a first result; (b) a second addition and subtraction device operating to perform a second arithmetic function on the n-most significant bits of each of said operands to obtain a second result; and (c) an evaluation circuit coupled to the second addition and subtraction device to evaluate the second result in respect of a first predetermined condition to determine a normalization amount for the first result of said first addition and subtraction device when the first predetermined condition is detected; (d) the evaluation circuit being coupled to the first addition and subtraction device to input the normalization amount.
Claim 2
Dependent Claim
122 words
An arithmetic logic device, which comprises: (a) a first addition and subtraction device operating to perform a first arithmetic function on operands to obtain a first result; (b) a second addition and subtraction device operating to perform a second arithmetic function on the n-most significant bits of each of said operands to obtain a second result; and (c) an evaluation circuit coupled to the second addition and subtraction device to evaluate the second result in respect of a first predetermined condition to determine a normalization amount for the first result of said first addition and subtraction device when the first predetermined condition is detected; (d) the evaluation circuit being coupled to the first addition and subtraction device to input the normalization amount.
Claim 3
Dependent Claim
31 words
An arithmetic logic device according to claim 1, further comprising an aligner connected to said first and second addition and subtraction devices for aligning the operands to thereby create guard bits.
Claim 4
Dependent Claim
29 words
An arithmetic logic device according to claim 2, wherein the first addition and subtraction device comprises an m-bit adder and a pre-round logic circuit connected to said m-bit adder.
Claim 5
Dependent Claim
65 words
An arithmetic logic device according to claim 3, wherein the pre-round logic circuit includes means for receiving the normalization amount from said evaluation circuit to shift a round bit in accordance with the normalization amount, means for adding the shifted round bit to said guard bits, and means for adding a carry-in bit into said m-bit adder , upon a second pre-determined condition being satisfied.
Claim 6
Dependent Claim
53 words
An arithmetic logic device according to claim 4, further comprising a multiplexer with inputs connected to an output of said m-bit adder and an output of said pre-round logic circuit, and a select line connected to said evaluation circuit for carrying signals to control said multiplexer in accordance with the first predetermined condition.
Claim 7
Dependent Claim
112 words
An arithmetic logic device according to claim 5 further comprising first and second parallel paths between said first addition and subtraction device and said multiplexer, wherein said first path includes: a priority encoder for determining the normalization amount; a normalization shifter for shifting an m-bit result of the m-bit adder in accordance with the normalization amount to produce a normalized result; and a further m-bit adder for adding said round bit to said normalized result; and wherein said second path includes a fast normalization shifter for shifting the m-bit result of the m-bit adder in accordance with the normalization amount from said evaluation circuit and the output of said pre-round logic circuit.
Claim 8
Dependent Claim
44 words
An arithmetic logic device according to claim 6, wherein said second addition and subtraction device includes a pair of parallel n-bit adders separately connected to said evaluation circuit, for respectively producing a sum and a sum plus a carry of said n-most significant bits.
Claim 9
Dependent Claim
67 words
An arithmetic logic device according to claim 7, wherein said evaluation circuit includes: a pair of priority encoders connected to said n-bit adders to respectively receive said sum and said sum plus a carry, each said priority encoder outputting an evaluation normalization amount; and a comparator for receiving and comparing said evaluation normalization amounts and outputting said signal to said multiplexer when said evaluation normalization amounts match.
Claim 10
Dependent Claim
22 words
An arithmetic logic device according to claim 8, wherein said first predetermined condition is the result of matching said evaluation normalization amounts.
Claim 11
Dependent Claim
31 words
An arithmetic logic device according to claim 9, wherein said second predetermined condition is a production of a carry-in bit when the shifted round bit is added to the guard bits.
Claim 12
Independent Claim
376 words
A method of operating a processor to perform floating point arithmetic operations on two floating point m-bit operands, the method comprising the steps of: (a) determining an alignment amount by which a first of said floating point m-bit operands must shift its lower ordered bits to align with a second of said floating point m-bit operands using an exponent subtractor; (b) storing in a first register an unaligned n-most significant bit slice from said second of said floating point m-bit operands; (c) producing an aligned n-most significant bit slice from said first of said floating point m-bit operands, in accordance with the alignment amount determined by the exponent subtractor, for storage in a second register; (d) aligning the first of the floating point m-bit operands and the second of the floating point m-bit operands in accordance with the alignment amount determined by the exponent subtractor; (e) storing in a third register as guard bits the lower ordered bits of said first of said floating point m-bit operands that were shifted by the alignment amount as a result of the alignment; (f) adding in two separate n-bit adders the aligned and unaligned n-most significant bit slices to produce a first and second sum, one of said n-bit adders receiving a carry bit; (g) calculating a first and second normalization amount from the first and second sums using a first and second priority encoder, respectively; (h) comparing in a comparator whether the first and second normalization amounts are equal, and when said first and second normalization amounts are equal: (i) calculating in a pre-round logic circuit a shifted round bit in accordance with one of the first and second normalization amounts, adding the shifted round bit to the guard bits to determine a first result and whether a carry bit is generated wherein said carry bit would be input to an m-bit adder, said m-bit adder adding the first and second of said floating point m-bit operands to produce a second result; (ii) shifting the second result in accordance with one of the first and second normalization amounts to produce a normalized result; (iii) shifting the first result into the lower ordered bits of the normalized result in accordance with one of the first and second normalization amounts.
Claim 13
Independent Claim
376 words
A method of operating a processor to perform floating point arithmetic operations on two floating point m-bit operands, the method comprising the steps of: (a) determining an alignment amount by which a first of said floating point m-bit operands must shift its lower ordered bits to align with a second of said floating point m-bit operands using an exponent subtractor; (b) storing in a first register an unaligned n-most significant bit slice from said second of said floating point m-bit operands; (c) producing an aligned n-most significant bit slice from said first of said floating point m-bit operands, in accordance with the alignment amount determined by the exponent subtractor, for storage in a second register; (d) aligning the first of the floating point m-bit operands and the second of the floating point m-bit operands in accordance with the alignment amount determined by the exponent subtractor; (e) storing in a third register as guard bits the lower ordered bits of said first of said floating point m-bit operands that were shifted by the alignment amount as a result of the alignment; (f) adding in two separate n-bit adders the aligned and unaligned n-most significant bit slices to produce a first and second sum, one of said n-bit adders receiving a carry bit; (g) calculating a first and second normalization amount from the first and second sums using a first and second priority encoder, respectively; (h) comparing in a comparator whether the first and second normalization amounts are equal, and when said first and second normalization amounts are equal: (i) calculating in a pre-round logic circuit a shifted round bit in accordance with one of the first and second normalization amounts, adding the shifted round bit to the guard bits to determine a first result and whether a carry bit is generated wherein said carry bit would be input to an m-bit adder, said m-bit adder adding the first and second of said floating point m-bit operands to produce a second result; (ii) shifting the second result in accordance with one of the first and second normalization amounts to produce a normalized result; (iii) shifting the first result into the lower ordered bits of the normalized result in accordance with one of the first and second normalization amounts.
References Cited (Backward Citations)
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Cited
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-30 | 1993-10-30 | 1994-05-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-30 | 1997-10-30 | 1998-05-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-30 | 2001-10-30 | 2002-05-01 | $7700.00 | Window Closed / Lapsed |