Patent US5143856A successfully refreshed from Google Patents.
US5143856A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing MES FET
Assignee: Toshiba Corp
•
Filing: 1988-08-29
•
Granted: 1992-09-01
•
Expires: 2008-08-29
Abstract
Abstract A GaAs epitaxial layer is formed on a semi-insulative GaAs substrate by use of a crystal growth technique which allows control on the order of atomic layer level. A metal film is formed on the GaAs epitaxial layer by use of the same crystal growth technique. Ions are implanted in source and drain high-concentration layer-forming regions, through the metal film, and are activated.
Inventors
- 👤 Hiroshi Iwasaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 21:07
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/0612; H10D30/0616; Y; Y10; Y10S; Y10S148/00; Y10S148/105; Y10S148/14
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
186 words
A method of manufacturing a MES FET, comprising the steps of: (a) forming a GaAs epitaxial layer of one conductivity type including a portion serving as a channel layer on a semi-insulative GaAs substrate, by use of a crystal growth technique which allows control at atomic layer level; (b) forming a first metal film including a portion serving as a Schottky gate electrode on the entire surface of said GaAs epitaxial layer, using the crystal growth technique which allows control at atomic layer level, immediately after the epitaxial layer-forming step and using an apparatus which is the same apparatus used in forming said GaAs epitaxial layer; (c) ion-implanting a high-concentration impurity of the cone conductivity type into source and drain high-concentration layer-forming regions, through said first metal film; (d) forming a second metal film on the entire surface of said first metal film; (e) performing activation annealing, after the ion-implanting step, while said first and second metal films remain on said epitaxial layer; and (f) patterning said first metal film to form said Schottky gate electrode by selectively etching said first metal film after activation annealing.
Claim 2
Independent Claim
186 words
A method of manufacturing a MES FET, comprising the steps of: (a) forming a GaAs epitaxial layer of one conductivity type including a portion serving as a channel layer on a semi-insulative GaAs substrate, by use of a crystal growth technique which allows control at atomic layer level; (b) forming a first metal film including a portion serving as a Schottky gate electrode on the entire surface of said GaAs epitaxial layer, using the crystal growth technique which allows control at atomic layer level, immediately after the epitaxial layer-forming step and using an apparatus which is the same apparatus used in forming said GaAs epitaxial layer; (c) ion-implanting a high-concentration impurity of the cone conductivity type into source and drain high-concentration layer-forming regions, through said first metal film; (d) forming a second metal film on the entire surface of said first metal film; (e) performing activation annealing, after the ion-implanting step, while said first and second metal films remain on said epitaxial layer; and (f) patterning said first metal film to form said Schottky gate electrode by selectively etching said first metal film after activation annealing.
Claim 3
Dependent Claim
23 words
A method according to claim 1, wherein the activation annealing is a capless annealing step which is performed in an arsino gas atmosphere.
Claim 4
Dependent Claim
85 words
A method according to claim 1, wherein the activation annealing is a cap annealing step wherein after a silicon oxide film, containing at least one element selected from the group consisting of phosphorus ions and arsenic ions, or a silicon nitride film containing neither of these ions, is formed on the substrate on which said first metal and second films are formed before the activation annealing step, the annealing is performed using said silicon oxide film or said silicon nitride film as a protective film.
References Cited (Backward Citations)
US4330343A
Cited
US4601095A
Cited
US4675709A
Cited
US4546540A
Cited
EP0112657A2
Cited
US4642879A
Cited
EP0123926A2
Cited
US4581076A
Cited
JPS6273673A
Cited
US4735913A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-09-01 | 1996-03-02 | 1996-09-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-09-01 | 2000-03-02 | 2000-09-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-09-01 | 2004-03-02 | 2004-09-01 | $7700.00 | Window Closed / Lapsed |