EP0112657A2
Expired / Lapsed
EP
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Field effect transistor and process for fabricating it
Assignee: Fujitsu Ltd
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Filing: 1983-11-25
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Granted: —
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Expires: 2003-11-25
Abstract
Abstract A field effect transistor (FET) comprises a source (8), a drain (9), and a control gate (6) on a compound semiconductor (e. g. GaAs) substrate (1). The FET has an ion-implanted channel layer (4) in the substrate adjacent the top surface thereof, below the control gate. The concentration of ions (i. e. the carrier concentration) in the channel layer has an maximum value at the top surface and decreases monotonically from that surface towards the inside thereof. This is achieved by ion implantation for the channel layer through an insulating layer (2) on the substrate. The insulating layer is preferably an A1 N layer, since such a layer has no adverse effects on the GaAs substrate during ion implantation and during subsequent heat treatment, and so allows higher uniformity of the threshold voltages of the FETs. FETs formed by this throug-implantation process have a high transconductance.
Inventors
- 👤 Haruo Kawata
- 👤 Hidetoshi Nishi
- 👤 Hiroyuki Onodera
- 👤 Naoki Yokoyama
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 21:32
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/206; H10P95/00; H10P95/90; H10P95/904; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/0612; H10D30/0616; H10D30/60; H10D30/67; H10D30/6729; H10D30/6737; H10D30/6738; H10D30/674; H10D30/675; H10D30/80; H10D30/87; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/60; H10D62/80; H10D62/85; H10D62/854; H10D64/00; H10D64/60; H10D64/64; H10P14/00; H10P14/60; H10P14/69; H10P14/694; H10P14/6943; H10P14/69433; H10P30/21; H10P30/212
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
74 words
A field effect transistor (FET) comprising a source (8), a drain (9), and a control gate (6) in and on a compound semiconductor substrate (1), characterised in that the FET has an ion-implanted channel layer (4) in the compound semiconductor substrate adjacent a surface thereof, below the control gate, the concentration of ions in the channel layer having an maximum value at said surface and monotonically decreasing from said surface towards the inside thereof.
Claim 2
Dependent Claim
74 words
A field effect transistor (FET) comprising a source (8), a drain (9), and a control gate (6) in and on a compound semiconductor substrate (1), characterised in that the FET has an ion-implanted channel layer (4) in the compound semiconductor substrate adjacent a surface thereof, below the control gate, the concentration of ions in the channel layer having an maximum value at said surface and monotonically decreasing from said surface towards the inside thereof.
Claim 3
Dependent Claim
18 words
An FET according to Claim 1, characterised in that the compound semiconductor substrate (1) is of gallium arsenide.
Claim 4
Dependent Claim
19 words
An FET according to Claim 1 or Claim 2, characterised in that the channel layer (4) is silicon ion-implanted.
Claim 5
Dependent Claim
34 words
An FET according to any preceding claim, characterised by a maximum concentration of silicon ions, 1x10 17 cm -3 to 4.0 x 10 cm , at the top surface of the channel layer (4).
Claim 6
Dependent Claim
18 words
An FET according to any preceding claim, characterised in that the control gate (6) is of tungsten silicide.
Claim 7
Dependent Claim
28 words
An FET according to any preceding claim, characterised in that edges of the source (8) and drain (9) align with opposite edges of the control gate (6), respectively.
Claim 8
Dependent Claim
29 words
An FET according to any preceding claim, characterised in that the FET has a transconductance of 270 mS/mm to 300 mS/mm with a control gate (6) of 1µm length.
Claim 9
Dependent Claim
131 words
A process for fabricating an FET comprising a source (8), a drain (9), and a control gate (6) in and on a compound semiconductor substrate (1), characterised by the steps of forming an insulating layer (2) on a surface of the compound semiconductor substrate; ion implanting through the insulating layer into a layer in the compound semiconductor substrate adjacent said surface; and heat treating the ion-implanted compound semiconductor substrate to form a channel layer (4) adjacent said surface thereof by activating the ions; wherein the conditions of the formation of the insulating layer, ion implantation, and heat treatment are controlled so that the concentration of ions in the channel layer (4) has a maximum value at said surface and monotonically decreases from said surface towards the inside of the channel layer.
Claim 10
Dependent Claim
131 words
A process for fabricating an FET comprising a source (8), a drain (9), and a control gate (6) in and on a compound semiconductor substrate (1), characterised by the steps of forming an insulating layer (2) on a surface of the compound semiconductor substrate; ion implanting through the insulating layer into a layer in the compound semiconductor substrate adjacent said surface; and heat treating the ion-implanted compound semiconductor substrate to form a channel layer (4) adjacent said surface thereof by activating the ions; wherein the conditions of the formation of the insulating layer, ion implantation, and heat treatment are controlled so that the concentration of ions in the channel layer (4) has a maximum value at said surface and monotonically decreases from said surface towards the inside of the channel layer.
Claim 11
Dependent Claim
18 words
A process according to Claim 8, characterised in that the compound semiconductor substrate (1) is of gallium arsenide.
Claim 12
Dependent Claim
19 words
A process according to Claim 9, characterised in that, in the step of ion implantation, silicon ions are implanted.
Claim 13
Dependent Claim
30 words
A process according to Claim 10, characterised in that, in the step of forming the insulating layer (2), an aluminium nitride layer is formed on the gallium arsenide substrate (1).
Claim 14
Dependent Claim
36 words
A process according to Claim 11, characterised in that, after the step of ion implantation and before the step of heat treatment, a second insulating layer (5) is deposited on to the aluminium nitride layer (2).
Claim 15
Dependent Claim
19 words
A process according to Claim 12, characterised in that said second insulating layer (5) is an aluminium nitride layer.
Claim 16
Dependent Claim
81 words
A process according to any one of Claims 8 to 12, characterised in that in the step of forming the insulating layer, an aluminium nitride layer (2) 50 to 200nm thick is formed; in the step of ion implantation, silicon ions are implanted at 20 to 100 keV and 1x 1 0 17 to 4x10 18 cm -2 ; and in the step of heat treatment, the temperature is held at 700°C to 1000 0 C for 1 to 300 minutes.
Claim 17
Dependent Claim
63 words
A process according to Claim 14, characterised in that in the step of forming the insulating layer (2), an aluminium nitride layer 55nm thick is formed; in the step of ion implantation, silicon ions are implanted at 59 keV and 4 x 10 12 cm -2 ; and in the step of heat treatment, the temperature is held at 850°C for 20 minutes.
Claim 18
Dependent Claim
63 words
A process according to Claim 14, characterised in that in the step of forming the insulating layer (2), an aluminium nitride layer 30nm thick is formed; in the step of ion implantation, silicon ions are implanted at 32 keV and 6 x 10 12 cm -2 ; and in the step of heat treatment, the temperature is held at 850°C for 20 minutes.
Claim 19
Dependent Claim
35 words
A process according to any one of Claims 12 to 16, characterised in that said second insulating layer (5) is of Si0 2 , Si 3 N 4 , or Al 2 0 3 .
References Cited (Backward Citations)
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