Dynamic ram, having an improved large capacitance

Claim 2

A dynamic RAM comprising: a semiconductor substrate; first and second MOS transistors, each having a source, a drain, and a gate, said source and drain being formed in said substrate; a first insulating film formed on said first and second MOS transistors; a first electrode, having first and second surfaces and formed over said first insulation film, for accumulating an electrical charge, said first electrode extending through a first hole made in said first insulating film and connected to one of the source and drain of said first MOS transistor; a second electrode, having third and fourth surfaces and formed over said first insulation film, for accumulating an electrical charge, said second electrode extending through a second hole made in said first insulation film and connected to one of the source and drain of said second MOS transistor, and at least one part of said second electrode being spaced apart from, located above, and overlapping part of said first electrode, the one part of said second electrode overlapping a part of said first electrode being over said first and second MOS transistors formed in said semiconductor substrate; first and second capacitor-insulating films encapsulating the first and second surfaces of said first electrode and the third and fourth surfaces of said second electrode, respectively, and a capacitor electrode formed on said first and second capacitor-insulating films and having a portion interposed between the overlapping parts of said first and second electrodes, said capacitor electrode facing the first and second surfaces of said first electrode with said first capacitor-insulating film interposed between said first and second surfaces, and said capacitor electrode facing the third and fourth surfaces of said second electrode with said second capacitor-insulating film interposed between said third and fourth surfaces and said capacitor electrode, one part of said capacitor electrode being over said first and second MOS transistors formed in said semiconductor substrate.

Claim 3

The dynamic RAM according to claim 1, wherein groups of MOS transistors identical to said first and second MOS transistors are formed in said semiconductor substrate, and a plurality of electrodes identical to said first and second electrodes are arranged in an alternating pattern.

Claim 4

The dynamic RAM according to claim 1, wherein a space is formed between said first capacitor-insulating film and said first insulating film, and a part of said capacitor electrode is interposed in said space between said first capacitor-insulating film and said first insulation film.

Claim 5

The dynamic RAM according to claim 1, wherein a surface of said first electrode which opposes said capacitor electrode has the same area as a surface of said second electrode which opposes said capacitor electrode.

Claim 6

A dynamic RAM comprising: a semiconductor substrate; first and second MOS transistors, each having a source, a drain, and a gate which functions as a word line, said source and drain being formed in said substance, one of said source and drain of said first MOS transistor being integrally formed with one of said source and drain of said second MOS transistor; a first insulation film formed on said first and second MOS transistors; a bit line having a contact portion extending through a first contact hole made in said first insulation film and connected to said one of the source and drain of said first MOS transistor, said bit line extending across the word linkes with an offset against a position of the contact portion; a second insulation film formed on the contact portion of said bit line; a first electrode, having first and second surfaces and formed over said first and second insulation films, for accumulating an electrical charge, said first electrode extending through a second contact hole made in said first and second insulation films and connected to the other of the source and drain of said first MOS transistor; a second electrode, having third and fourth surfaces and formed over said first and second insulation films, for accumulating an electrical charge, said second electrode extending through a third contact hole made in the first and second insulation films and connected to the other of the source and drain of said second MOS transistor, and at least one part of said second electrode being spaced apart from, located above, and overlapping part of said first electrode, the one part of said second electrode overlapping a part of said first electrode being over said first and second MOS transistors formed in said semiconductor substrate; first and second capacitor-insulating films encapsulating the first and second surfaces of said first electrode and the third and fourth surfaces of said second electrode, respectively; and a capacitor electrode formed on said first and second capacitor-insulating films and having a portion interposed between the overlapping parts of said first and second electrodes, said capacitor electrode facing the first and second surfaces of said first electrode with said first capacitor-insulating film interposed between said first and second surfaces, and said capacitor electrode facing the third and fourth surfaces of said second electrode with said second capacitor-insulating film interposed between said third and fourth surfaces, one part of said capacitor electrode being over said first and second MOS transistors formed in said semiconductor substrate.

Claim 7

A dynamic RAM comprising: a semiconductor substrate; first and second MOS transistors, each having a source, a drain, and a gate which functions as a word line, said source and drain being formed in said substance, one of said source and drain of said first MOS transistor being integrally formed with one of said source and drain of said second MOS transistor; a first insulation film formed on said first and second MOS transistors; a bit line having a contact portion extending through a first contact hole made in said first insulation film and connected to said one of the source and drain of said first MOS transistor, said bit line extending across the word linkes with an offset against a position of the contact portion; a second insulation film formed on the contact portion of said bit line; a first electrode, having first and second surfaces and formed over said first and second insulation films, for accumulating an electrical charge, said first electrode extending through a second contact hole made in said first and second insulation films and connected to the other of the source and drain of said first MOS transistor; a second electrode, having third and fourth surfaces and formed over said first and second insulation films, for accumulating an electrical charge, said second electrode extending through a third contact hole made in the first and second insulation films and connected to the other of the source and drain of said second MOS transistor, and at least one part of said second electrode being spaced apart from, located above, and overlapping part of said first electrode, the one part of said second electrode overlapping a part of said first electrode being over said first and second MOS transistors formed in said semiconductor substrate; first and second capacitor-insulating films encapsulating the first and second surfaces of said first electrode and the third and fourth surfaces of said second electrode, respectively; and a capacitor electrode formed on said first and second capacitor-insulating films and having a portion interposed between the overlapping parts of said first and second electrodes, said capacitor electrode facing the first and second surfaces of said first electrode with said first capacitor-insulating film interposed between said first and second surfaces, and said capacitor electrode facing the third and fourth surfaces of said second electrode with said second capacitor-insulating film interposed between said third and fourth surfaces, one part of said capacitor electrode being over said first and second MOS transistors formed in said semiconductor substrate.

Claim 8

The dynamic RAM according to claim 5, wherein groups of MOS transistors identical to said first and second MOS transistors are formed in said semiconductor substrate, and a plurality of electrodes identical to said first and second electrodes are arranged in an alternating pattern.

Claim 9

The dynamic RAM according to claim 5, wherein a space is formed between said first capacitor-insulating film and said first insulating film, and a part of said capacitor electrode is interposed in said space between said first capacitor-insulating film and said first insulation film.

Claim 10

The dynamic RAM according to claim 5, wherein a surface of said first electrode which opposes said capacitor electrode has the same area as a surface of said second electrode which opposes said capacitor electrode.

Claim 11

The dynamic RAM according to claim 5, wherein said first bit line is connected to said one of the source and drain of said first MOS transistor by a first pad electrode, said first electrode is connected to said other of the source and drain of said first MOS transistor by a second pad electrode, said second bit line is connected to said one of the source and drain of said second MOS transistor by a third pad electrode, and said second electrode is connected to said other of the source and drain of said second MOS transistor by a fourth pad electrode.

Claim 12

The dynamic RAM according to claim 5, wherein said first and second bit lines are formed on an element-isolating region, and intersects at right angles with the word lines formed of the gates of said first and second MOS transistors.

Claim 13

The dynamic RAM according to claim 5, wherein said first bit line is connected to said one of the source and drain of said first MOS transistors by a first pad electrode, said second bit line is connected to said one of the source and drain of said second MOS transistor by a second pad electrode, and said first and second pad electrodes extends onto an element isolation region.

Claim 14

The dynamic RAM according to claim 5, wherein said each one of the source and drain of said first and second MOS transistors have regions extending toward said word line, and said first and second bit lines are connected to the regions.