Semiconductor memory device

Claim 2

A semiconductor memory device, characterized by comprising: a) a semiconductor substrate (11) of a first conductivity type; b) an insulating film (12) for isolation between cells provided on the surface of said semiconductor substrate (11); c) a first electrode layer (16) provided on the surface of said substrate (11) partitioned by said isolation insulating film (12) through a first insulating film (15); d) a hole (17) penetrating through said first electrode layer (26) and said first insulating film (15); and e) a second electrode layer (19) provided at least on said first electrode layer (16) and within said hole (17) through a second insulating film (18), a portion of said second electrode layer (19) being connected to said substrate through said hole (17).

Claim 3

A semiconductor memory device as set forth in claim 1, wherein a first diffusion region (20) of a second conductivity type is provided in an area near said surface of said semiconductor substrate (11) to which an electrode (19) is connected.

Claim 4

A semiconductor memory device as set forth in claim 1, wherein a second diffusion region (22) of a second conductivity type is provided in an area near said surface of said semiconductor substrate (11) below said first insulating film (15).

Claim 5

A semiconductor memory device as set forth in claim 2 or 3, wherein a third diffusion region of said first conductivity type is provided in said semiconductor substrate (11) below said first and second diffusion regions.

Claim 6

A semiconductor memory device as set forth in claim 1, wherein a groove (31) is digged in said semiconductor substrate (11), an oxide film (32) is provided onto the inner surface of said groove (31), and a capacitor electrode layer (19) is provided at least within said groove through said oxide film (32).

Claim 7

A semiconductor memory device as set forth in claim 1, wherein a transfer gate electrode (23) is provided on said second electrode layer (19).

Claim 8

A semiconductor memory device as set forth in claim 1, wherein a transfer gate electrode is provided below said first electrode layer (16).

Claim 9

A semiconductor memory device, characterized by comprising: a) a semiconductor substrate (10); b) a first insulating film (110) formed on said semiconductor substrate (101); c) a first electrode layer (111) formed on said first insulating film (110), a predetermined voltage being applied to said first electrode layer (111); d) a second insulating film (112) formed on said first electrode layer (111); e) a second electrode layer (113) formed on said second insulating film (112); f) a transfer transistor (106) for transferring charge to said semiconductor substrate (101) and said second electrode layer (113); whereby said first insulating film (110), a portion of said semiconductor substrate (101) below said first insulating film (110) and said first electrode layer (111) define a first capacitor, and said second insulating film (112), a portion of said first electrode layer (111) below said second insulating film (112) and said second electrode layer (113) define a second capacitor, thus using said first and second capacitors as the cell capacitor of the memory.

Claim 10

A semiconductor memory device, characterized by comprising: a) a semiconductor substrate (10); b) a first insulating film (110) formed on said semiconductor substrate (101); c) a first electrode layer (111) formed on said first insulating film (110), a predetermined voltage being applied to said first electrode layer (111); d) a second insulating film (112) formed on said first electrode layer (111); e) a second electrode layer (113) formed on said second insulating film (112); f) a transfer transistor (106) for transferring charge to said semiconductor substrate (101) and said second electrode layer (113); whereby said first insulating film (110), a portion of said semiconductor substrate (101) below said first insulating film (110) and said first electrode layer (111) define a first capacitor, and said second insulating film (112), a portion of said first electrode layer (111) below said second insulating film (112) and said second electrode layer (113) define a second capacitor, thus using said first and second capacitors as the cell capacitor of the memory.

Claim 11

A semiconductor memory device as set forth in claim 8, wherein said transfer transistor (106) is comprised of a field-effect transistor formed on said semiconductor substrate (101), one electrode (107b) of said transistor being buried into said semiconductor substrate and connected thereto, said second electrode layer (113) being connected to said one electrode (107b) of said transistor (106).

Claim 12

A semiconductor memory device as set forth in claim 9, wherein said electrode (107b) of said transistor (106) buried into said semiconductor substrate is comprised of a doped layer of a conductivity type opposite to said semiconductor substrate (101).

Claim 13

A semiconductor memory device as set forth in claim 8, 9 or 10, wherein said semiconductor substrate (10) comprises a doped layer (115) of a conductivity type opposite to said semiconductor substrate (101), and a heavily doped layer (116) of the same conductivity type as said semiconductor substrate (101) being provided below said doped layer (115) provided below said first insulating film (110).

Claim 14

A semiconductor memory device as set forth in claim 8, 9, 10 or 11, wherein said semiconductor substrate (101) is provided with a groove (131) for increasing the capacity of a capacitor.

Claim 15

A semiaonductor memory device as set forth in claim 8, wherein a groove (131) is digged into said semiconductor substrate (101) , a capacitor oxide film (132) being provided on the side walls of said groove (131), said electrode (107b) of said transfer transistor (106) being provided on the bottom wall of said groove (131).