US5138407A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Transistor made of 3-5 group semiconductor materials on a silicon substrate
Assignee: Thales SA
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Filing: 1990-12-05
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Granted: 1992-08-11
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Expires: 2010-12-05
Abstract
Abstract The present invention concerns a transistor of semiconductor materials of the 3-5 group on silicon of the type comprising a silicon substrate, at least one layer of semi-insulating 3-5 material and several doped layers of 3-5 group semiconductor material in which is defined at least one conducting channel equipped with a gate metallization, each channel being situated between two access regions alternately known as source and drain, each source and drain regions with a metallization, one of the two access regions to a channel being electrically and thermally connected to the silicon substrate. In accordance with the invention, the transistor comprises between the silicon substrate and the semi-insulating layer of 3-5 group semiconductor material, at least one buffer layer of intrinsic silicon.
Inventors
- 👤 Jean-Pierre Hirtz
- 👤 Marie-Noelle Charasse
- 👤 Thierry Pacou
- 👤 Alain Bosella
- 👤 Pierre Briere
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 19:25
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/80; H10D62/83; H10D62/82; H10D64/00; H10D64/20; H10D64/23; H10D64/251; H10D64/60; H10D64/62; H10W; H10W15/00; H10W15/01; H10W40/00; H10W40/10; H10P; H10P14/00; H10P14/20; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/32; H10P14/3202; H10P14/3204; H10P14/3211; H10P14/3214; H10P14/3221; H10P14/3242; H10P14/3244; H10P14/3248; H10P14/34; H10P14/3402; H10P14/3414; H10P14/3418; H10P14/3421
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
95 words
A transistor comprising a silicon substrate, at least one layer of semi-insulating 3-5 group material and several doped layers of 3-5 group semiconductor material through which is defined at least one conducting channel equipped with a gate metallization, each channel being situated between two access regions known alternately as source and drain, each with a metallization, one of the two regions of access to a channel being electrically and thermally connected to the silicon substrate, between the silicon substrate and the semi-insulating layer of 3-5 group material, at least one buffer layer of intrinsic silicon.
Claim 2
Dependent Claim
95 words
A transistor comprising a silicon substrate, at least one layer of semi-insulating 3-5 group material and several doped layers of 3-5 group semiconductor material through which is defined at least one conducting channel equipped with a gate metallization, each channel being situated between two access regions known alternately as source and drain, each with a metallization, one of the two regions of access to a channel being electrically and thermally connected to the silicon substrate, between the silicon substrate and the semi-insulating layer of 3-5 group material, at least one buffer layer of intrinsic silicon.
Claim 3
Dependent Claim
18 words
The transistor according to claim 1, wherein the buffer layer of silicon is at least 10 μm thick.
Claim 4
Dependent Claim
19 words
The transistor according to claim 2, wherein the layer of semi-insulating 3-5 group material is about 4 μm thick.
Claim 5
Dependent Claim
21 words
The transistor according to claim 1, wherein the substrate is selected from the group consisting of N+ and P+ doped silicon.
Claim 6
Dependent Claim
54 words
The transistor according to claim 1, wherein the connection between one of the access regions and the silicon substrate is formed by a metal core which crosses the layers of 3-5 group semiconductor material and intrinsic silicon and makes an ohmic contact on the substrate at the interface with the layer of intrinsic silicon.
Claim 7
Dependent Claim
38 words
The transistor according to claim 1, wherein the 3-5 group semiconductor materials are selected from the group consisting of binary compositions of Ga, As, Al, In and P, and ternary compositions of Ga, As, Al, In and P.
Claim 8
Dependent Claim
96 words
A transistor having 3-5 group semiconductor material on silicon comprising a silicon substrate, at least one layer of semi-insulating 3-5 group material and several doped layers of 3-5 group semiconductor material with at least one conducting channel having a gate metallization, each channel being situated between source and drain regions, each source and drain region, with a metallization, one of said source and drain regions being electrically and thermally connected to the silicon substrate and having between the silicon substrate and the semi-insulating layer of 3-5 group material, at least one buffer layer of intrinsic silicon.
Claim 9
Dependent Claim
96 words
A transistor having 3-5 group semiconductor material on silicon comprising a silicon substrate, at least one layer of semi-insulating 3-5 group material and several doped layers of 3-5 group semiconductor material with at least one conducting channel having a gate metallization, each channel being situated between source and drain regions, each source and drain region, with a metallization, one of said source and drain regions being electrically and thermally connected to the silicon substrate and having between the silicon substrate and the semi-insulating layer of 3-5 group material, at least one buffer layer of intrinsic silicon.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-08-11 | 1996-02-10 | 1996-08-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-08-11 | 2000-02-10 | 2000-08-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-08-11 | 2004-02-10 | 2004-08-11 | $7700.00 | Window Closed / Lapsed |