Method of fabricating a semiconductor structure having MOS and bipolar devices

Claim 1

A method of fabricating a semiconductor structure having MOS and bipolar devices comprising the steps of: providing an isolation structure having MOS and bipolar active areas including doped wells; forming a collector region in said bipolar active area forming a first semiconductor layer over said MOS and bipolar active areas; forming an active base region in said bipolar active area well; forming a dielectric layer on said first semiconductor layer over a portion of said bipolar active area and forming a window in said dielectric layer extending to said first semiconductor layer; forming a second semiconductor layer over said MOS and bipolar active areas; forming a gate electrode on said MOS active area and emitter and collector electrodes on said bipolar active area, said gate, emitter and collector electrodes being formed from said first and second semiconductor layers and said emitter electrode extending into said window; doping said emitter and collector electrodes; forming self-aligned source and drain regions in said MOS active area; and diffusing an emitter region into said bipolar active area well from said emitter electrode through said window.

Claim 2

A method of fabricating a semiconductor structure having MOS and bipolar devices comprising the steps of: providing an isolation structure having MOS and bipolar active areas including doped wells; forming a collector region in said bipolar active area forming a first semiconductor layer over said MOS and bipolar active areas; forming an active base region in said bipolar active area well; forming a dielectric layer on said first semiconductor layer over a portion of said bipolar active area and forming a window in said dielectric layer extending to said first semiconductor layer; forming a second semiconductor layer over said MOS and bipolar active areas; forming a gate electrode on said MOS active area and emitter and collector electrodes on said bipolar active area, said gate, emitter and collector electrodes being formed from said first and second semiconductor layers and said emitter electrode extending into said window; doping said emitter and collector electrodes; forming self-aligned source and drain regions in said MOS active area; and diffusing an emitter region into said bipolar active area well from said emitter electrode through said window.

Claim 8

A method of fabricating a semiconductor structure having complementary MOS and bipolar devices comprising the steps of: providing an isolation structure having a complementary MOS active area including a P doped well and an N doped well and a bipolar active area including a doped well; forming a collector region in said bipolar active area well; forming a first silicon layer over said MOS and bipolar active areas; forming an active base region in said bipolar active area well; forming a dielectric layer on said first silicon layer over a portion of said bipolar active area and forming a window in said dielectric layer extending to said first silicon layer; forming dielectric spacers in said window and forming an oxide lens between said spacers; removing said spacers and forming slots extending through said first silicon layer in said window where said dielectric spacers were formerly disposed; forming link base regions in said bipolar active area well through said slots; filling said slots with a dielectric material; forming a second silicon layer over said MOS and bipolar active areas; forming gate electrodes on said P doped well and said N doped well of said MOS active area and emitter and collector electrodes on said bipolar active area well, said gate, emitter and collector electrodes being formed from said first and second silicon layers and wherein said emitter electrode extends into said window; doping said emitter and collector electrodes; forming self-aligned N type source and drain regions in said P doped well of said MOS active area and self-aligned P type source and drain regions in said N doped well of said MOS active area; forming an extrinsic base region in said bipolar active area; and diffusing an emitter region into said bipolar active area well from said emitter electrode through said window.

Claim 9

A method of fabricating a semiconductor structure having complementary MOS and bipolar devices comprising the steps of: providing an isolation structure having a complementary MOS active area including a P doped well and an N doped well and a bipolar active area including a doped well; forming a collector region in said bipolar active area well; forming a first silicon layer over said MOS and bipolar active areas; forming an active base region in said bipolar active area well; forming a dielectric layer on said first silicon layer over a portion of said bipolar active area and forming a window in said dielectric layer extending to said first silicon layer; forming dielectric spacers in said window and forming an oxide lens between said spacers; removing said spacers and forming slots extending through said first silicon layer in said window where said dielectric spacers were formerly disposed; forming link base regions in said bipolar active area well through said slots; filling said slots with a dielectric material; forming a second silicon layer over said MOS and bipolar active areas; forming gate electrodes on said P doped well and said N doped well of said MOS active area and emitter and collector electrodes on said bipolar active area well, said gate, emitter and collector electrodes being formed from said first and second silicon layers and wherein said emitter electrode extends into said window; doping said emitter and collector electrodes; forming self-aligned N type source and drain regions in said P doped well of said MOS active area and self-aligned P type source and drain regions in said N doped well of said MOS active area; forming an extrinsic base region in said bipolar active area; and diffusing an emitter region into said bipolar active area well from said emitter electrode through said window.

Claim 15

A method of fabricating a BICMOS structure having a resistive region comprising the steps of: providing an isolation structure having a complementary MOS active area including a P well and an N well, a bipolar active area having a doped well and a resistor area; implanting a collector region into said doped well of said bipolar active area; forming a first polysilicon layer over said MOS and bipolar active areas and said resistor area; forming an active base region in said doped well of said bipolar active area; forming a dielectric layer on said first polysilicon layer over a portion of said bipolar active area and forming a widow in said dielectric layer that extends to said first polysilicon layer; forming first dielectric spacers in said window abutting sidewalls of said window and forming an oxide lens on said first polysilicon layer between said first spacers; removing said first spacers and forming slots through said first polysilicon layer in said window where said first spacers were formerly disposed; implanting link base regions in said bipolar active area through said slots; forming second dielectric spacers in said slots; forming a second polysilicon layer over said MOS and bipolar active areas and said resistor area; forming gate electrodes on said P well and said N well of said MOS active area and emitter and collector electrodes on said bipolar active area, said gate, emitter and collector electrodes being formed from said first and second polysilicon layers and wherein said emitter electrode extends into said window; doping said emitter and collector electrodes; doping the portions of said first and second polysilicon layers disposed over said resistor area to form a resistive region; doping at least one end of said resistive region to have a lesser resistivity than a central portion of said resistive region; doping at least portions of the first polysilicon layer adjacent said emitter contact to form a base electrode; implanting P type source and drain regions in said N well and N type source and drain regions in said P well; and diffusing an emitter region into said bipolar active area well from said emitter electrode through said window.

Claim 16

A method of fabricating a BICMOS structure having a resistive region comprising the steps of: providing an isolation structure having a complementary MOS active area including a P well and an N well, a bipolar active area having a doped well and a resistor area; implanting a collector region into said doped well of said bipolar active area; forming a first polysilicon layer over said MOS and bipolar active areas and said resistor area; forming an active base region in said doped well of said bipolar active area; forming a dielectric layer on said first polysilicon layer over a portion of said bipolar active area and forming a widow in said dielectric layer that extends to said first polysilicon layer; forming first dielectric spacers in said window abutting sidewalls of said window and forming an oxide lens on said first polysilicon layer between said first spacers; removing said first spacers and forming slots through said first polysilicon layer in said window where said first spacers were formerly disposed; implanting link base regions in said bipolar active area through said slots; forming second dielectric spacers in said slots; forming a second polysilicon layer over said MOS and bipolar active areas and said resistor area; forming gate electrodes on said P well and said N well of said MOS active area and emitter and collector electrodes on said bipolar active area, said gate, emitter and collector electrodes being formed from said first and second polysilicon layers and wherein said emitter electrode extends into said window; doping said emitter and collector electrodes; doping the portions of said first and second polysilicon layers disposed over said resistor area to form a resistive region; doping at least one end of said resistive region to have a lesser resistivity than a central portion of said resistive region; doping at least portions of the first polysilicon layer adjacent said emitter contact to form a base electrode; implanting P type source and drain regions in said N well and N type source and drain regions in said P well; and diffusing an emitter region into said bipolar active area well from said emitter electrode through said window.