Circuit containing integrated bipolar and complementary MOS transistors on a common substrate

Claim 1

In a method of manufacturing bipolar and complementary MOS transistors on a common doped substrate, the steps comprising: generating wells in said substrate of a conductivity type opposite to that of said substrate, etching trenches in said wells, and filling the trenches with doped polysilicon having said conductivity type opposite to that of said substrate.

Claim 4

A method for the manufacture of bipolar and complementary MOS transistors on a common doped substrate which comprises: providing buried zones in said substrate of a conductivity type opposite to that of said substrate, applying an epitaxial layer over said substrate of the same conductivity type as said substrate, generating wells in said substrate of a conductivity type opposite to that of said substrate, etching trenches in said wells down to the depth of said epitaxial layer, filling the trenches with doped polysilicon having a conductivity type opposite to that of said substrate, and generating bipolar and MOS transistors between said trenches.

Claim 5

A method for the manufacture of bipolar and complementary MOS transistors on a common doped substrate which comprises: providing buried zones in said substrate of a conductivity type opposite to that of said substrate, applying an epitaxial layer over said substrate of the same conductivity type as said substrate, generating wells in said substrate of a conductivity type opposite to that of said substrate, etching trenches in said wells down to the depth of said epitaxial layer, filling the trenches with doped polysilicon having a conductivity type opposite to that of said substrate, and generating bipolar and MOS transistors between said trenches.

Claim 7

A method for the manufacture of bipolar and complementary MOS transistors on a common silicon substrate which comprises: forming buried n + doped zones in a p-doped semiconductor substrate, applying a p-doped epitaxial layer over the entire surface, generating n-wells in said substrate by implanting n-doping ions therein, driving in the implanted n-doping ions while simultaneously oxidizing the surface of the n-well regions, implanting boron ions for the manufacture of a surface distal region of the channel zone of the n-channel MOS transistors, implanting boron ions for doping the field oxide regions of the n-channel MOS transistors, forming field oxide regions to separate the various active regions in said substrate, generating etched trenches in the lateral edge regions of said wells down to the depth of said p-doped epitaxial layer, depositing an intermediate oxide in said trenches, selectively etching away said intermediate oxide to leave an oxide layer on the sidewalls of said trenches, depositing polycrystalline silicon in said trenches, doping the polycrystalline silicon with n + doping ions, forming the base zone of the bipolar transistors by boron ion implantation, oxidizing the exposed surface to generate a gate oxide, implanting boron ions for doping the channel regions of the MOS transistors, depositing a gate material to form gate electrodes in the MOS transistors, depositing a silicon oxide intermediate oxide layer on the surface, simultaneously forming the source/drain regions of the n-channel MOS transistors, the emitter and the n collector contact of the bipolar transistors by implantation of n-doping ions, simultaneously forming the source/drain regions of the p-channel MOS transistors and the p + base contact of the bipolar transistors by boron ion implantation, and applying terminal electrodes to the transistor elements.

Claim 8

A method for the manufacture of bipolar and complementary MOS transistors on a common silicon substrate which comprises: forming buried n + doped zones in a p-doped semiconductor substrate, applying a p-doped epitaxial layer over the entire surface, generating n-wells in said substrate by implanting n-doping ions therein, driving in the implanted n-doping ions while simultaneously oxidizing the surface of the n-well regions, implanting boron ions for the manufacture of a surface distal region of the channel zone of the n-channel MOS transistors, implanting boron ions for doping the field oxide regions of the n-channel MOS transistors, forming field oxide regions to separate the various active regions in said substrate, generating etched trenches in the lateral edge regions of said wells down to the depth of said p-doped epitaxial layer, depositing an intermediate oxide in said trenches, selectively etching away said intermediate oxide to leave an oxide layer on the sidewalls of said trenches, depositing polycrystalline silicon in said trenches, doping the polycrystalline silicon with n + doping ions, forming the base zone of the bipolar transistors by boron ion implantation, oxidizing the exposed surface to generate a gate oxide, implanting boron ions for doping the channel regions of the MOS transistors, depositing a gate material to form gate electrodes in the MOS transistors, depositing a silicon oxide intermediate oxide layer on the surface, simultaneously forming the source/drain regions of the n-channel MOS transistors, the emitter and the n collector contact of the bipolar transistors by implantation of n-doping ions, simultaneously forming the source/drain regions of the p-channel MOS transistors and the p + base contact of the bipolar transistors by boron ion implantation, and applying terminal electrodes to the transistor elements.