Integrated semiconductor transistor structure with epitaxial contact to the buried sub-collector including fabrication method therefor

Abstract

Abstract This disclosure is directed to an improved integrated semiconductor transistor device which has the feature of a heavily doped epitaxial semiconductor region in contact with a buried sub-collector region. Additional features include dielectric sidewall isolation combined with PN junction isolation between the substrate and the collector portion of the transistor. The epitaxial contact to the buried sub-collector region is formed simultaneous with the formation of polycrystalline silicon filler material that fills in the dielectric isolation moat or channel located around the sides of individual electrically isolated transistor devices in order to achieve a planar surface structure. Another feature of the transistor device is the use of a base region that extends completely across and in contact with the sidewalls of the dielectric isolation moat. Preferably, the emitter region also extends across and in contact with three of the four of the sidewalls of the dielectric isolation moat. In this manner, transistor devices can be made very small with external electrical metal contacts made to the emitter region, the base region, and to the heavily doped epitaxial semiconductor region that is in contact with the buried sub-collector region. This epitaxial contact region to the buried sub-collector region is located within a portion of the polycrystalline silicon filler material that is bounded by the dielectric isolation sidewall material.

Inventors

• 👤 Donald K Roberson

Bibliographic Details