Abstract This disclosure is directed to an improved integrated semiconductor transistor device which has the feature of a heavily doped epitaxial semiconductor region in contact with a buried sub-collector region. Additional features include dielectric sidewall isolation combined with PN junction isolation between the substrate and the collector portion of the transistor. The epitaxial contact to the buried sub-collector region is formed simultaneous with the formation of polycrystalline silicon filler material that fills in the dielectric isolation moat or channel located around the sides of individual electrically isolated transistor devices in order to achieve a planar surface structure. Another feature of the transistor device is the use of a base region that extends completely across and in contact with the sidewalls of the dielectric isolation moat. Preferably, the emitter region also extends across and in contact with three of the four of the sidewalls of the dielectric isolation moat. In this manner, transistor devices can be made very small with external electrical metal contacts made to the emitter region, the base region, and to the heavily doped epitaxial semiconductor region that is in contact with the buried sub-collector region. This epitaxial contact region to the buried sub-collector region is located within a portion of the polycrystalline silicon filler material that is bounded by the dielectric isolation sidewall material.
AN INTERGRATED SEMICONDUCTOR STRUCTURE COMPRISING A BODY OF SEMICONDUCTOR MATERIAL HAVING AT LEAST ONE SEMICONDUCTOR TRANSISTOR DEVICE FORMED THEREIN HAVING AN EMITTER REGION, A BASE REGION AND A BURIED SUB-COLLECTOR REGION IN SAID BODY OF SEMICONDUCTOR MATERIAL: A GROOVE HAVING SIDEWALLS FORMED IN SAID BODY OF SEMICONDUCTOR MATERIAL AND SURROUNDING SAID SEMICONDUCTOR TRANSISTOR DEVICE: DIELECTRIC ISOLATION MEANS ON THE SIDEWALLS OF SAID GROOVE FOR INSULATING SAID SEMICONDUCTOR TRANSISTOR DEVICE FROM THE REMAINDER OF SAID INTEGRATED SEMICONDUCTOR STRUCTURE: POLYCRYSTALLINE SEMICONDUCTOR MATERIAL IN SAID GROOVE: AND A BODY OF HIGH CONDUCTIVITY MONOCRYSTALLINE SEMICONDUCTOR MATERIAL OF THE SAME CONDUCTIVITY TYPE AS SAID BURIED SUB-COLLECTOR REGION EXTENDING THROUGH SAID GROOVE WITHIN AND CONTIGUOUS WITH SAID POLYCRYSTALLINE SEMICONDUCTOR MATERIAL SAID BODY OF HIGH CONDUCTIVITY MONOCRYSTALLINE SEMICONDUCTOR MATERIAL PASSING THROUGH SAID DIELECTRIC ISOLATION MEANS TO AND TO CONTACT SAID BURIED SUBCOLLECTOR REGION.
Claim 2
Dependent Claim
136 words
AN INTERGRATED SEMICONDUCTOR STRUCTURE COMPRISING A BODY OF SEMICONDUCTOR MATERIAL HAVING AT LEAST ONE SEMICONDUCTOR TRANSISTOR DEVICE FORMED THEREIN HAVING AN EMITTER REGION, A BASE REGION AND A BURIED SUB-COLLECTOR REGION IN SAID BODY OF SEMICONDUCTOR MATERIAL: A GROOVE HAVING SIDEWALLS FORMED IN SAID BODY OF SEMICONDUCTOR MATERIAL AND SURROUNDING SAID SEMICONDUCTOR TRANSISTOR DEVICE: DIELECTRIC ISOLATION MEANS ON THE SIDEWALLS OF SAID GROOVE FOR INSULATING SAID SEMICONDUCTOR TRANSISTOR DEVICE FROM THE REMAINDER OF SAID INTEGRATED SEMICONDUCTOR STRUCTURE: POLYCRYSTALLINE SEMICONDUCTOR MATERIAL IN SAID GROOVE: AND A BODY OF HIGH CONDUCTIVITY MONOCRYSTALLINE SEMICONDUCTOR MATERIAL OF THE SAME CONDUCTIVITY TYPE AS SAID BURIED SUB-COLLECTOR REGION EXTENDING THROUGH SAID GROOVE WITHIN AND CONTIGUOUS WITH SAID POLYCRYSTALLINE SEMICONDUCTOR MATERIAL SAID BODY OF HIGH CONDUCTIVITY MONOCRYSTALLINE SEMICONDUCTOR MATERIAL PASSING THROUGH SAID DIELECTRIC ISOLATION MEANS TO AND TO CONTACT SAID BURIED SUBCOLLECTOR REGION.
Claim 3
Dependent Claim
51 words
The structure of claim 1 wherein said body of semiconductor material is of opposite conductivity to the conductivity of said buried sub-collector region of said semiconductor transistor device and forms a P-N junction therewith, said PN junction isolating said semiconductor transistor device from the remaining portion of said integrated semiconductor structure.
Claim 4
Dependent Claim
15 words
The structure of claim 2 wherein said semiconductor transistor device is an NPN transistor device.
Claim 5
Dependent Claim
16 words
The structure of claim 2 wherein said dielectric isolation means comprises a layer of silicon dioxide.
Claim 6
Dependent Claim
30 words
The structure of claim 4 wherein said polycrystalline semiconductor material comprises polycrystalline silicon material, said high conductivity body of monocrystalline semiconductor material being in contact with said polycrystalline silicon material.
Claim 7
Dependent Claim
15 words
The structure of claim 5 wherein said moat having a substantially V-shaped cross sectional configuration.
Claim 8
Dependent Claim
43 words
The structure of claim 1 wherein the entire perimeter of the base region of said semiconductor transistor device being in contact with said dielectric isolation means; the emitter region of said semiconductor transistor device being in contact with said dielectric sidewall isolation means.
Claim 9
Dependent Claim
30 words
The structure of claim 1 including separate metal contacts to the emitter region, the base region, and the high conductivity body that is in contact with said buried sub-collector region.