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US4803175A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of fabricating a bipolar semiconductor device with silicide contacts

Assignee: NXP USA Inc
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Filing: 1987-09-14
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Granted: 1989-02-07
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Expires: 2007-09-14
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Abstract

Abstract A method for making a bipolar semiconductor device having silicide contacts which is compatible with the processing steps used in the fabrication of MOS devices. The present invention includes the use of sidewall spacers to limit the self-aligned implants of the extrinsic base and the silicide contact. The device is annealed so that the diffusion of the polysilicon layer which forms the emitter may be controlled. Since the emitter size may be controlled, the emitter to base contact area may be reduced resulting in improved device performance.

Inventors

  • 👤 Antonio R. Alvarez
  • 👤 James A. Kirchgessner

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 19:20
CPC Classifications
H; H10; H10P; H10P76/00; H10P76/40; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171; Y; Y10; Y10S; Y10S148/00; Y10S148/01; Y10S148/011

Claims Analysis

Total Claims: 16
Claim 1
Independent Claim 144 words
A method of processing a bipolar semiconductor device comprising the steps of: providing a substrate; isolating a device region on said substrate; forming a first dielectric layer on said substrate; forming an active base in said device region of said substrate; defining an emitter opening in said first dielectric layer; depositing a polysilicon layer on said first dielectric layer and in said emitter opening; doping said polysilicon layer; masking and etching said polysilicon layer so that said polysilicon extends beyond said emitter opening; etching said first dielectric layer so that only the portion covered by said etched polysilicon layer remains; forming silicide contacts on said polysilicon layer and said base; forming a second dielectric layer on said device region; etching contact openings in said second dielectric layer, said contact openings extending to said silicide contacts; and metallizing said contact openings to create external contacts.
Claim 2
Independent Claim 144 words
A method of processing a bipolar semiconductor device comprising the steps of: providing a substrate; isolating a device region on said substrate; forming a first dielectric layer on said substrate; forming an active base in said device region of said substrate; defining an emitter opening in said first dielectric layer; depositing a polysilicon layer on said first dielectric layer and in said emitter opening; doping said polysilicon layer; masking and etching said polysilicon layer so that said polysilicon extends beyond said emitter opening; etching said first dielectric layer so that only the portion covered by said etched polysilicon layer remains; forming silicide contacts on said polysilicon layer and said base; forming a second dielectric layer on said device region; etching contact openings in said second dielectric layer, said contact openings extending to said silicide contacts; and metallizing said contact openings to create external contacts.
Claim 3
Dependent Claim 18 words
The method of claim 1 wherein the polysilicon layer and the active base are of opposite conductivity types.
Claim 4
Dependent Claim 14 words
The method of claim 2 further comprising the step of forming an extrinsic base.
Claim 5
Dependent Claim 22 words
The method of claim 3 wherein the steps of forming an active base and forming an extrinsic base are performed by implantation.
Claim 6
Dependent Claim 26 words
The method of claim 4 wherein a self-aligned implant is performed to implant the extrinsic base during or directly following the etching of the polysilicon layer.
Claim 7
Dependent Claim 40 words
The method of claim 3 wherein after the etching of the polysilicon layer, a conformal dielectric layer is formed over the device region and the conformal dielectric layer and the first dielectric layer are etched to provide for sidewall spacers.
Claim 8
Dependent Claim 23 words
The method of claim 6 wherein a self-aligned implant is performed to implant the extrinsic base following the processing of the sidewall spacers.
Claim 9
Dependent Claim 14 words
The method of claim 1 wherein the formation of the silicide contacts is self-aligned.
Claim 10
Dependent Claim 18 words
The method of claim 1 wherein the device is annealed prior to the formation of the silicide contacts.
Claim 11
Dependent Claim 39 words
The method of claim 6 wherein the first dielectric layer, the second dielectric layer and the conformal dielectric layer may be one of the group comprising an oxide, a nitride and a combination of an oxide and a nitride.
Claim 12
Independent Claim 185 words
A method of processing a bipolar semiconductor device comprising the steps of: providing a substrate; isolating a device region on said substrate; forming a first dielectric layer on said substrate; forming an active bse in said device region of said substrate; defining an emitter opening in said first dielectric layer; depositing a polysilicon layer on said first dielectric layer and in said emitter opening; doping said polysilicon layer; masking and etching said polysilicon layer so that said polysilicon extends beyond said emitter opening; forming a conformal dielectric layer on said etched polysilicon layer and said first dielectric layer; etching said conformal dielectric layer and said first dielectric layer to form sidewall spacers; forming an extrinsic base in said substrate using said sidewall spacers for self-alignment; annealing said device so that an emitter is diffused from said polysilicon layer into said active base; forming silicide contacts using said sidewall spacers for self-alignment; forming a second dielectric layer on said device region, etching contact opening in said second dielectric layer, said contact openings extending to said silicide contacts; and metallizing said contact openings to create external contacts.
Claim 13
Independent Claim 185 words
A method of processing a bipolar semiconductor device comprising the steps of: providing a substrate; isolating a device region on said substrate; forming a first dielectric layer on said substrate; forming an active bse in said device region of said substrate; defining an emitter opening in said first dielectric layer; depositing a polysilicon layer on said first dielectric layer and in said emitter opening; doping said polysilicon layer; masking and etching said polysilicon layer so that said polysilicon extends beyond said emitter opening; forming a conformal dielectric layer on said etched polysilicon layer and said first dielectric layer; etching said conformal dielectric layer and said first dielectric layer to form sidewall spacers; forming an extrinsic base in said substrate using said sidewall spacers for self-alignment; annealing said device so that an emitter is diffused from said polysilicon layer into said active base; forming silicide contacts using said sidewall spacers for self-alignment; forming a second dielectric layer on said device region, etching contact opening in said second dielectric layer, said contact openings extending to said silicide contacts; and metallizing said contact openings to create external contacts.
Claim 14
Dependent Claim 18 words
The method of claim 11 wherein the polysilicon layer and the active base are of opposite conductivity types.
Claim 15
Dependent Claim 40 words
The method of claim 12 wherein the first dielectric layer, the second dielectric layer, and the conformal dielectric layer may be one of the group comprising an oxide, a n itride and a combination of an oxide and a nitride.
Claim 16
Dependent Claim 22 words
The method of claim 12 wherein the steps of forming an active base and forming an extrinsic base are performed by implantation.

References Cited (Backward Citations)

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US3940288A Cited
US4188707A Cited
US4259680A Cited
US4609568A Cited
US4698127A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-02-07 1992-08-08 1993-02-07 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-02-07 1996-08-08 1997-02-07 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-02-07 2000-08-08 2001-02-07 $7700.00 Window Closed / Lapsed

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