Bi-cmos circuit with high-speed active pull-down output currents

Claim 2

A BI-CMOS circuit comprising: a first transistor made from an N-channel MOS transistor that is turned on and off in response to the logic state of an input signal and that supplies a first current to a base of an output transistor when the first transistor is turned on; and an active pull-down current supplying means connected to the gate electrode of said first transistor and for supplying a second current, which is active pull-down current, to the base of said output transistor so that said first and second currents can be supplied to the base of said output transistor, wherein said active pull-down current supplying means includes a second transistor made from a p-channel MOS transistor and having a gate electrode connected to the gate electrode of said first transistor, a third transistor made from an N-channel MOS transistor and having a gate electrode connected to the gate electrode of said second transistor, the third transistor being connected in series with said second transistor, and a fourth transistor made from a bipolar-transistor and having a base connected to a source of said third transistor and an emitter connected to the base of said output transistor.

Claim 3

A Bi-CMOS circuit as set forth in claim 1, wherein said second transistor is substantially identical in area with said third transistor.

Claim 4

A Bi-CMOS circuit as set forth in claim 1, wherein said second transistor is greater in area than said third transistor.

Claim 5

A BI-CMOS circuit comprising: a first transistor made from an N-channel MOS transistor that is turned on and off in response to the logic state of an input signal and that supplies a first current to the base of an output transistor when the first transistor is turned on; and an active pull-down current supplying means connected to the gate electrode of said first transistor and for supplying a second current, which is active pull-down current, to the base of said output transistor so that said first and second currents can be supplied to the base of said output transistor, wherein said active pull-down current supplying means includes a second transistor made from a p-channel MOS transistor and having a gate electrode connected to the gate electrode of said first transistor, a third transistor made from an N-channel MOS transistor and having a gate electrode connected to the gate electrode of said second transistor, a source of the third transistor being connected in series with a drain of said second transistor, a fourth transistor made from a p-channel MOS transistor, a fifth transistor made from an N-channel MOS transistor and having a gate electrode connected to a gate electrode of said fourth transistor, a source of the fifth transistor being connected in series with a drain of said fourth transistor, a source of said second transistor being connected to a source of said fourth transistor, and a sixth transistor made from a bipolar transistor and having a base connected to said fifth transistor and an emitter connected to the base of said output transistor.

Claim 6

A BI-CMOS circuit comprising: a first transistor made from an N-channel MOS transistor that is turned on and off in response to the logic state of an input signal and that supplies a first current to the base of an output transistor when the first transistor is turned on; and an active pull-down current supplying means connected to the gate electrode of said first transistor and for supplying a second current, which is active pull-down current, to the base of said output transistor so that said first and second currents can be supplied to the base of said output transistor, wherein said active pull-down current supplying means includes a second transistor made from a p-channel MOS transistor and having a gate electrode connected to the gate electrode of said first transistor, a third transistor made from an N-channel MOS transistor and having a gate electrode connected to the gate electrode of said second transistor, a source of the third transistor being connected in series with a drain of said second transistor, a fourth transistor made from a p-channel MOS transistor, a fifth transistor made from an N-channel MOS transistor and having a gate electrode connected to a gate electrode of said fourth transistor, a source of the fifth transistor being connected in series with a drain of said fourth transistor, a source of said second transistor being connected to a source of said fourth transistor, and a sixth transistor made from a bipolar transistor and having a base connected to said fifth transistor and an emitter connected to the base of said output transistor.