US4970414A
Expired / Lapsed
US
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TTL-level-output interface circuit
Assignee: SILICON CONNECTIONS Corp 6160 LUSK BLVD STE C-204 SAN DIEGO CA A CORP OF
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Filing: 1989-07-07
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Granted: 1990-11-13
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Expires: 2009-07-07
Abstract
Abstract A TTL-level-output interface circuit includes a biCMOS inverter coupled between a voltage supply terminal and a ground terminal; a first npn transistor coupled between the voltage supply terminal and a TTL interface terminal and a second npn transistor connected in series with the first npn transistor between the TTL interface terminal and the ground terminal; an n phi network coupled between the TTL output terminal and the base of the second npn transistor by an n-channel MOSFET, which has its gate connected to the inverter input terminal. When a high input signal is applied to the inverter input terminal, the n-channel MOSFET couples the n phi network to the base of the second npn transistor, in order both to limit the base current of the second npn transistor in order to prevent saturation of the second npn transistor, and to enable current to be conducted to the base of the second npn transistor 56 through the n phi network from a load connected to the TTL output terminal, for enabling the second npn transistor to conduct current from the TTL interface terminal to the ground terminal. A p-channel MOSFET is coupled between the voltage supply terminal and the junction of the n phi network with the n-channel MOSFET. The p-channel MOSFET has its gate connected to the inverter output terminal and functions as a switchable current source for providing a minimum base current to the second npn transistor if there is no load connected to the TTL output terminal when a high input signal is applied at the inverter input terminal.
Inventors
- 👤 Robert N. Ruth, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 16:51
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/013; H03K19/0175; H03K19/017509; H03K19/017518
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
300 words
A TTL interface circuit, comprising an inverter coupled between a voltage supply terminal and a ground terminal, and having an input terminal and an output terminal; a first npn transistor coupled between the voltage supply terminal and a TTL interface terminal and a second npn transistor connected in series with the first npn transistor between the TTL interface terminal and the ground terminal; wherein the first npn transistor has a base coupled to the inverter output terminal for enabling the first npn transistor to conduct current between the voltage supply terminal and the TTL interface terminal when a low input signal is applied at the inverter input terminal, and for clamping the first npn transistor in a non-conductive state when a high input signal is applied at the inverter input terminal; wherein the second npn transistor has a base coupled to the ground terminal through a first switching means that is coupled to the inverter for clamping the second npn transistor in a nonconductive state when a low input signal is applied at the inverter input terminal; and limiting means coupled between the TTL output terminal and the base of the second npn transistor for limiting the base current of the second npn transistor in order to prevent saturation of the second npn transistor; wherein circuit means are coupled between the TTL output terminal and the base of the second npn transistor by a second switching means that is coupled to the inverter for enabling current to be conducted to the base of the second npn transistor through said circuit means from a load connected to the TTL output terminal when a high input signal is applied at the inverter input terminal, for enabling the second npn transistor to conduct current from the TTL interface terminal to the ground terminal.
Claim 2
Dependent Claim
300 words
A TTL interface circuit, comprising an inverter coupled between a voltage supply terminal and a ground terminal, and having an input terminal and an output terminal; a first npn transistor coupled between the voltage supply terminal and a TTL interface terminal and a second npn transistor connected in series with the first npn transistor between the TTL interface terminal and the ground terminal; wherein the first npn transistor has a base coupled to the inverter output terminal for enabling the first npn transistor to conduct current between the voltage supply terminal and the TTL interface terminal when a low input signal is applied at the inverter input terminal, and for clamping the first npn transistor in a non-conductive state when a high input signal is applied at the inverter input terminal; wherein the second npn transistor has a base coupled to the ground terminal through a first switching means that is coupled to the inverter for clamping the second npn transistor in a nonconductive state when a low input signal is applied at the inverter input terminal; and limiting means coupled between the TTL output terminal and the base of the second npn transistor for limiting the base current of the second npn transistor in order to prevent saturation of the second npn transistor; wherein circuit means are coupled between the TTL output terminal and the base of the second npn transistor by a second switching means that is coupled to the inverter for enabling current to be conducted to the base of the second npn transistor through said circuit means from a load connected to the TTL output terminal when a high input signal is applied at the inverter input terminal, for enabling the second npn transistor to conduct current from the TTL interface terminal to the ground terminal.
Claim 3
Dependent Claim
95 words
A TTL interface circuit according to claim 1, wherein the limiting means and the circuit means comprise a singular nφ network coupled in series with the second switching means between the TTL output terminal and the base of the second npn transistor for both limiting the base current of the second npn transistor in order to prevent saturation of the second npn transistor, and conducting current to the base of the second npn transistor from said load connected to the TTL output terminal when a high input signal is applied at the inverter input terminal.
Claim 4
Dependent Claim
71 words
A TTL interface circuit according to claim 2, further comprising a switchable current source coupled between the voltage supply terminal and the junction of the nφ network with the second switching means, and coupled to the inverter for providing a minimum base current to the second npn transistor if there is no load connected to the TTL output terminal when a high input signal is applied at the inverter input terminal.
Claim 5
Dependent Claim
64 words
A TTL interface circuit according to claim 2, wherein the second switching means comprises a MOSFET coupled in series between the nφ network and the base of the second npn transistor, and having a gate coupled to the inverter for connecting the nφ network to the base of the second npn transistor when a high input signal is applied to the inverter input terminal.
Claim 6
Dependent Claim
15 words
A TTL interface circuit according to claim 4, wherein the inverter is a CMOS inverter.
Claim 7
Dependent Claim
16 words
A TTL interface circuit according to claim 5, wherein the CMOS inverter is a biCMOS inverter.
Claim 8
Dependent Claim
75 words
A TTL interface circuit according to claim 5, further comprising a MOSFET coupled between the voltage supply terminal and the junction of the nφ network with the MOSFET of the second switching means, and having a gate coupled to the inverter for providing a minimum base current to the second npn transistor if there is no load connected to the TTL output terminal when a high input signal is applied at the inverter input terminal.
Claim 9
Dependent Claim
75 words
A TTL interface circuit according to claim 4, further comprising a MOSFET coupled between the voltage supply terminal and the junction of the nφ network with the MOSFET of the second switching means, and having a gate coupled to the inverter for providing a minimum base current to the second npn transistor if there is no load connected to the TTL output terminal when a high input signal is applied at the inverter input terminal.
Claim 10
Dependent Claim
71 words
A TTL interface circuit according to claim 1, further comprising a switchable current source coupled between the voltage supply terminal and the junction of the circuit means with the second switching means, and coupled to the inverter for providing a minimum base current to the second npn transistor if there is no load connected to the TTL output terminal when a high input signal is applied at the inverter input terminal.
Claim 11
Dependent Claim
76 words
A TTL interface circuit according to claim 9, wherein the switchable current source comprises a MOSFET coupled between the voltage supply terminal and the junction of the circuit means with the second switching means, and having a gate coupled to the inverter for providing a minimum base current to the second npn transistor if there is no load connected to the TTL output terminal when a high input signal is applied at the inverter input terminal.
Claim 12
Dependent Claim
64 words
A TTL interface circuit according to claim 1, wherein the second switching means comprises a MOSFET coupled in series between the circuit means and the base of the second npn transistor, and having a gate coupled to the inverter for connecting the circuit means to the base of the second npn transistor when a high input signal is applied to the inverter input terminal.
Claim 13
Dependent Claim
15 words
A TTL interface circuit according to claim 1, wherein the inverter is a CMOS inverter.
Claim 14
Dependent Claim
16 words
A TTL interface circuit according to claim 12, wherein the CMOS inverter is a biCMOS inverter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-11-12 | 1994-05-14 | 1994-11-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-11-12 | 1998-05-14 | 1998-11-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-11-12 | 2002-05-14 | 2002-11-13 | $7700.00 | Window Closed / Lapsed |