Logic circuit used in standard IC or CMOS logic level

Claim 2

A logic circuit used in a standard IC of CMOS logic level, comprising: signal input means for receiving input data; a signal output terminal; a first potential supply source; a second potential supply source; first and second bipolar transistors each having a base, collector, and emitter, the collector-emitter paths being serially connected to each other at a connection node between said first and second potential supply sources, the connection node of said first and second bipolar transistors being connected to said signal output terminal for setting the signal output terminal to a first potential level; first CMOS logic means having an input terminal connected to said signal input means and an output terminal connected to the base of said first bipolar transistor; second CMOS logic means having an input terminal connected to said signal input means and an output terminal connected to said signal output terminal, said second CMOS logic means being operative to change said first potential level of the signal output terminal to the potential level of one of said first and second potential supply sources; first switching means connected between said signal output terminal and the base of said second bipolar transistor, operative to be switched OFF at times when the input data is set at a potential level corresponding to the level for rendering said first bipolar transistor conductive, and operative to be switched ON at times when the input data is set at a potential level corresponding to the level for rendering said first bipolar transistor nonconductive; and second switching means connected between said second potential supply source and the base of said second bipolar transistor, operative to be switched OFF at times when the input data is set at a potential level corresponding to the level for rendering said first bipolar transistor conductive, and operative to be switched ON at times when the input data is set at a potential level corresponding to the level for rendering said first bipolar transistor nonconductive, wherein said signal input means is a signal input terminal, each of said first and second CMOS logic means is a CMOS inverter and said first switching means comprises an N channel MOSFET whose drain-source path is connected between said signal output terminal and the base of said second bipolar transistor, and whose gate is connected to said signal input terminal.

Claim 3

A logic circuit according to claim 1, wherein said second switching means comprises an N channel MOSFET whose drain-source path is connected between the base of said second bipolar transistor and said second potential supply source, and whose base is connected to an output terminal of said first CMOS inverter.

Claim 4

A logic circuit according to claim 1, which further comprises a CMOS inverter having input terminal connected to said signal input means and wherein said second switching means includes an N channel MOSFET having a drain-source path connected between the base of said second bipolar transistor and said second potential supply source, and having a gate connected to an output terminal of said CMOS inverter.

Claim 5

A logic circuit used in a standard IC of CMOS logic level, comprising: signal input means for receiving input data; a signal output terminal; a first potential supply source; a second potential supply source; first and second bipolar transistors each having a base, collector, and emitter, the collector-emitter paths being serially connected to each other at a connection node between said first and second potential supply sources, the connection node of said first and second bipolar transistors being connected to said signal output terminal for setting the signal output terminal to a first potential level; first CMOS logic means having an input terminal connected to said signal input means and an output terminal connected to the base of said first bipolar transistor; second CMOS logic means having an input terminal connected to said signal input means and an output terminal connected to said signal output terminal, said second CMOS logic means being operative to change said first potential level of the signal output terminal to the potential level of one of said first and second potential supply sources; first switching means connected between said signal output terminal and the base of said second bipolar transistor, operative to be switched OFF at times when the input data is set at a potential level corresponding to the level for rendering said first bipolar transistor conductive, and operative to be switched ON at times when the input data is set at a potential level corresponding to the level for rendering said first bipolar transistor nonconductive; second switching means connected between said second potential supply source and the base of said second bipolar transistor, operative to be switched OFF at times when the input data is set at a potential level corresponding to the level for rendering said first bipolar transistor conductive, and operative to be switched ON at times when the input data is set at a potential level corresponding to the level for rendering said first bipolar transistor nonconductive; a first diode whose anode and cathode are connected to said signal input means and said first potential supply source; a second diode whose cathode and anode are connected to said signal input means and said second potential supply source; a third diode whose anode and cathode are connected to said signal output terminal and said first potential supply source; a fourth diode whose cathode and anode are connected to said signal output terminal and said second potential supply source; a first resistor connected between said signal input means and said first CMOS logic means; a second resistor connected between said input means and said second CMOS logic means; and a third resistor connected between said signal input means and said first switching means.

Claim 6

A logic circuit used in a standard IC of CMOS logic level, comprising: signal input means for receiving input data; a signal output terminal; a first potential supply source; a second potential supply source; first and second bipolar transistors each having a base, collector, and emitter, the collector-emitter paths being serially connected to each other at a connection node between said first and second potential supply sources, the connection node of said first and second bipolar transistors being connected to said signal output terminal for setting the signal output terminal to a first potential level; first CMOS logic means having an input terminal connected to said signal input means and an output terminal connected to the base of said first bipolar transistor; second CMOS logic means having an input terminal connected to said signal input means and an output terminal connected to said signal output terminal, said second CMOS logic means being operative to change said first potential level of the signal output terminal to the potential level of one of said first and second potential supply sources; first switching means connected between said signal output terminal and the base of said second bipolar transistor, operative to be switched OFF at times when the input data is set at a potential level corresponding to the level for rendering said first bipolar transistor conductive, and operative to be switched ON at times when the input data is set at a potential level corresponding to the level for rendering said first bipolar transistor nonconductive; second switching means connected between said second potential supply source and the base of said second bipolar transistor, operative to be switched OFF at times when the input data is set at a potential level corresponding to the level for rendering said first bipolar transistor conductive, and operative to be switched ON at times when the input data is set at a potential level corresponding to the level for rendering said first bipolar transistor nonconductive; a first diode whose anode and cathode are connected to said signal input means and said first potential supply source; a second diode whose cathode and anode are connected to said signal input means and said second potential supply source; a third diode whose anode and cathode are connected to said signal output terminal and said first potential supply source; a fourth diode whose cathode and anode are connected to said signal output terminal and said second potential supply source; a first resistor connected between said signal input means and said first CMOS logic means; a second resistor connected between said input means and said second CMOS logic means; and a third resistor connected between said signal input means and said first switching means.

Claim 7

A logic circuit used in a standard IC of CMOS logic level, comprising: signal input means for receiving input data; a signal output terminal; a first potential supply source; a second potential supply source; first and second bipolar transistors each having a base, collector, and emitter, the collector-emitter paths being serially connected to each other at a connection node between said first and second potential supply sources, the connection node of said first and second bipolar transistors being connected to said signal output terminal for setting the signal output terminal to a first potential level; first CMOS logic means having an input terminal connected to said signal input means and an output terminal connected to the base of said first bipolar transistor; second CMOS logic means having an input terminal connected to said signal input means and an output terminal connected to said signal output terminal, said second CMOS logic means being operative to change said first potential level of the signal output terminal to the potential level of one of said first and second potential supply sources; first switching means connected between said signal output terminal and the base of said second bipolar transistor, operative to be switched OFF at times when the input data is set at a potential level corresponding to the level for rendering said first bipolar transistor conductive, and operative to be switched ON at times when the input data is set at a potential level corresponding to the level for rendering said first bipolar transistor nonconductive; and second switching means connected between said second potential supply source and the base of said second bipolar transistor, operative to be switched OFF at times when the input data is set at a potential level corresponding to the level for rendering said first bipolar transistor conductive, and operative to be switched ON at times when the input data is set at a potential level corresponding to the level for rendering said first bipolar transistor nonconductive, wherein said signal input means includes n (which is an integer greater than 1) signal input terminals, each of said first and second CMOS logic means comprises an n-input NAND gate, and said first switching means comprises n number of N channel MOSFETs whose drain-source paths are serially connected between said signal output terminal and the base of said second bipolar transistor, and whose gates are respectively connected to said signal input terminals.

Claim 8

A logic circuit used in a standard IC of CMOS logic level, comprising: signal input means for receiving input data; a signal output terminal; a first potential supply source; a second potential supply source; first and second bipolar transistors each having a base, collector, and emitter, the collector-emitter paths being serially connected to each other at a connection node between said first and second potential supply sources, the connection node of said first and second bipolar transistors being connected to said signal output terminal for setting the signal output terminal to a first potential level; first CMOS logic means having an input terminal connected to said signal input means and an output terminal connected to the base of said first bipolar transistor; second CMOS logic means having an input terminal connected to said signal input means and an output terminal connected to said signal output terminal, said second CMOS logic means being operative to change said first potential level of the signal output terminal to the potential level of one of said first and second potential supply sources; first switching means connected between said signal output terminal and the base of said second bipolar transistor, operative to be switched OFF at times when the input data is set at a potential level corresponding to the level for rendering said first bipolar transistor conductive, and operative to be switched ON at times when the input data is set at a potential level corresponding to the level for rendering said first bipolar transistor nonconductive; and second switching means connected between said second potential supply source and the base of said second bipolar transistor, operative to be switched OFF at times when the input data is set at a potential level corresponding to the level for rendering said first bipolar transistor conductive, and operative to be switched ON at times when the input data is set at a potential level corresponding to the level for rendering said first bipolar transistor nonconductive, wherein said signal input means includes n (which is an integer greater than 1) signal input terminals, each of said first and second CMOS logic means comprises an n-input NAND gate, and said first switching means comprises n number of N channel MOSFETs whose drain-source paths are serially connected between said signal output terminal and the base of said second bipolar transistor, and whose gates are respectively connected to said signal input terminals.

Claim 9

A logic circuit used in a standard IC of CMOS logic level, comprising: signal input means for receiving input data; a signal output terminal; a first potential supply source; a second potential supply source; first and second bipolar transistors each having a base, collector, and emitter, the collector-emitter paths being serially connected to each other at a connection node between said first and second potential supply sources, the connection node of said first and second bipolar transistors being connected to said signal output terminal for setting the signal output terminal to a first potential level; first CMOS logic means having an input terminal connected to said signal input means and an output terminal connected to the base of said first bipolar transistor; second CMOS logic means having an input terminal connected to said signal input means and an output terminal connected to said signal output terminal, said second CMOS logic means being operative to change said first potential level of the signal output terminal to the potential level of one of said first and second potential supply sources; first switching means connected between said signal output terminal and the base of said second bipolar transistor, operative to be switched OFF at times when the input data is set at a potential level corresponding to the level for rendering said first bipolar transistor conductive, and operative to be switched ON at times when the input data is set at a potential level corresponding to the level for rendering said first bipolar transistor nonconductive; and second switching means connected between said second potential supply source and the base of said second bipolar transistor, operative to be switched OFF at times when the input data is set a potential level corresponding to the level for rendering said first bipolar transistor conductive, and operative to be switched ON at times when the input data is set at a potential level corresponding to the level for rendering said first bipolar transistor nonconductive, wherein said signal input means includes n (which is an integer greater than 1) signal input terminals, each of said first and second CMOS logic means comprises an n-input NOR gate, and said first switching means comprising n number of N channel MOSFETs whose drain-source paths are connected in parallel between said signal output terminal and the base of said second bipolar transistor, and whose gates are respectively connected to said signal input terminals.

Claim 10

A logic circuit used in a standard IC of CMOS logic level, comprising: signal input means for receiving input data; a signal output terminal; a first potential supply source; a second potential supply source; first and second bipolar transistors each having a base, collector, and emitter, the collector-emitter paths being serially connected to each other at a connection node between said first and second potential supply sources, the connection node of said first and second bipolar transistors being connected to said signal output terminal for setting the signal output terminal to a first potential level; first CMOS logic means having an input terminal connected to said signal input means and an output terminal connected to the base of said first bipolar transistor; second CMOS logic means having an input terminal connected to said signal input means and an output terminal connected to said signal output terminal, said second CMOS logic means being operative to change said first potential level of the signal output terminal to the potential level of one of said first and second potential supply sources; first switching means connected between said signal output terminal and the base of said second bipolar transistor, operative to be switched OFF at times when the input data is set at a potential level corresponding to the level for rendering said first bipolar transistor conductive, and operative to be switched ON at times when the input data is set at a potential level corresponding to the level for rendering said first bipolar transistor nonconductive; and second switching means connected between said second potential supply source and the base of said second bipolar transistor, operative to be switched OFF at times when the input data is set a potential level corresponding to the level for rendering said first bipolar transistor conductive, and operative to be switched ON at times when the input data is set at a potential level corresponding to the level for rendering said first bipolar transistor nonconductive, wherein said signal input means includes n (which is an integer greater than 1) signal input terminals, each of said first and second CMOS logic means comprises an n-input NOR gate, and said first switching means comprising n number of N channel MOSFETs whose drain-source paths are connected in parallel between said signal output terminal and the base of said second bipolar transistor, and whose gates are respectively connected to said signal input terminals.