EP0072694A2
Expired / Lapsed
EP
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Transistor circuit
Assignee: Fujitsu Ltd
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Filing: 1982-08-16
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Granted: —
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Expires: 2002-08-16
Abstract
Abstract A transistor circuit includes a pull-down circuit (PD) which discharges electric charges stored at the base of an output transistor (Q2) of the circuit. The pull-down circuit (PD) comprises a control transistor (Q5), a two-terminal impedance means (TU) and a resistor (R4). The stored electric charges are discharged to a ground by way of the two-terminal unit (TU) and the resistor (R4). The stored electric charges are discharged selectively when the output transistor (Q2) is turned off, by the control transistor (Q5).
Inventors
- 👤 Tetsu Tanizawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 20:02
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/088; H03K19/01; H03K19/013; H03K19/0136
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
146 words
A transistor circuit comprising an input terminal; an output terminal; a phase-inverting transistor (Q1) having its base connected to the input terminal; first (Q2) and second (Q4) output transistors connected to the output terminal, the first and second output transistors being arranged so that they are of opposite conduction state and-are turned on and off in response to an output of the phase-inverting transistor (Q1); and a pull-down circuit (PD) for discharging electric charges stored at a base of the first output transistor (Q2), characterised in that the pull-down circuit comprises a control circuit (Q5) which has an output node (Pl) and which generates a signal having the same phase as the input signal at the output node (Pl) and a two terminal impedance means (TU) connected between the base of the first output transistor (Q2) and the output node (Pl) of the control circuit (Q5).
Claim 2
Dependent Claim
146 words
A transistor circuit comprising an input terminal; an output terminal; a phase-inverting transistor (Q1) having its base connected to the input terminal; first (Q2) and second (Q4) output transistors connected to the output terminal, the first and second output transistors being arranged so that they are of opposite conduction state and-are turned on and off in response to an output of the phase-inverting transistor (Q1); and a pull-down circuit (PD) for discharging electric charges stored at a base of the first output transistor (Q2), characterised in that the pull-down circuit comprises a control circuit (Q5) which has an output node (Pl) and which generates a signal having the same phase as the input signal at the output node (Pl) and a two terminal impedance means (TU) connected between the base of the first output transistor (Q2) and the output node (Pl) of the control circuit (Q5).
Claim 3
Dependent Claim
60 words
A transistor circuit according to claim 1, wherein the control circuit comprises a power supply line, a ground line, a control transistor (Q5) connected between the power supply line and the output node (Pl) for generating the signal having the same phase as the input signal, and a resistor (R4) connected between the output node (Pl) and the ground line.
Claim 4
Dependent Claim
30 words
A transistor circuit according to claim 2, wherein the control transistor (Q5) is of the same conductivity type as that of the phase-inverting transistor (Q1) connected to the input terminal.
Claim 5
Dependent Claim
38 words
A transistor circuit according to claim 2, wherein the control transistor (Q5) is of the opposite conductivity type to that of the phase-inverting transistor (Ql) and the base of the control transistor (Q5) receives the inverted input signal.
Claim 6
Dependent Claim
24 words
A transistor circuit according to any one of the preceding claims, wherein the two-terminal impedance means (TU) comprises a Schottky barrier diode (Figure 4A).
Claim 7
Dependent Claim
25 words
A transistor circuit according to any one of claims 1 to 4, wherein the two-terminal impedance means (TU) comprises a diode (Figure 4B or 4F).
Claim 8
Dependent Claim
25 words
A transistor circuit according to any one of claims 1 to 4, wherein the two-terminal impedance means (TU) comprises a capacitor, (Figure 4C or 4E).
Claim 9
Dependent Claim
26 words
A transistor circuit according to any one of claims 1 to 4, wherein the two-terminal impedance means (TU) comprises a resistor (Figure 4D, 4E or 4F).
Claim 10
Dependent Claim
29 words
A transistor circuit according to any one of claims 1 to 4, wherein the two-terminal impedance means (TU) comprises a capacitor and a resistor connected in parallel (Figure 4E).
Claim 11
Dependent Claim
30 words
-10. A transistor circuit according to any one of claims 1 to 4, wherein the two-terminal impedance means (TU) comprises a diode and a resistor connected in parallel (Figure 4F).
References Cited (Backward Citations)
No citation records indexed.
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