Floating point processor with high speed rounding circuit

Claim 2

A floating point processor responsive to input floating point numbers for performing floating point arithmetic operations on the input floating point numbers, comprising: a first arithmetic means for adding to or subtracting from a first fraction of a first floating point number, having an exponent larger than the exponent of the other floating point number, a second fraction of a second floating point number having a weight of corresponding bits equal to that of the first floating point number by being right shifted and the exponent is less than that of the first floating point number and for outputting the result of the addition or the subtraction; a second arithmetic means for performing the same one of adding and subtracting operations as said first arithmetic means effects on the first fraction and the sum of the second fraction and "1" and for outputting the result of the addition or the subtraction; an inverting means for reversing every bit of the output of said second arithmetic means; and a result selecting means for selecting the arithmetic operation from the outputs of said first and second arithmetic means and said inverting means.

Claim 3

A floating point processor as set forth in claim 1 which further comprises "carry for rounding" generation means for outputting a carry signal generated at a reference digital position when the rounding is performed at a predetermined digit, said carry signal indicating a carry obtained from parts of the first and the second fractions and data obtained at a guard bit, a round bit and sticky bit by making the weight of bit of the first floating point number equal to that of corresponding bit of the second floating point number, said result selecting means selecting one of the outputs of said first and second arithmetic means and said inverting means on the basis of the output of said "carry for rounding" generation means, a signal indicating one of the addition and the subtraction, the overflows and most significant bits in the outputs of said first and second arithmetic means.

Claim 4

A floating point processor responsive to input floating point numbers for performing floating point arithmetic operations on the input floating point numbers, comprising: first means for (a) performing a first operation wherein a first fraction of a first floating point number, having an exponent larger than the exponent of the other floating point number, is added to or subtracted from a second fraction of a second floating point number having (i) a weight of corresponding bits equal to that of the first floating point number by being right shift and (ii) an exponent less than that of the first floating point number, (b) deriving a first output that is the result of the addition or the subtraction of the first operation, (c) performing the same adding or subtracting operation as performed on the first fraction and the sum of the second fraction during the first operation and adding one to the resultant and (d) deriving a second output that is the result of operation (c); an inverting means for reversing every bit of the second output; and a result selecting means for selecting the arithmetic operation from the outputs of said first means and said inverting means.

Claim 5

A floating point processor responsive to input floating point numbers for performing floating point arithmetic operations on the input floating point numbers, comprising: first means for (a) performing a first operation wherein a first fraction of a first floating point number, having an exponent larger than the exponent of the other floating point number, is added to or subtracted from a second fraction of a second floating point number having (i) a weight of corresponding bits equal to that of the first floating point number by being right shift and (ii) an exponent less than that of the first floating point number, (b) deriving a first output that is the result of the addition or the subtraction of the first operation, (c) performing the same adding or subtracting operation as performed on the first fraction and the sum of the second fraction during the first operation and adding one to the resultant and (d) deriving a second output that is the result of operation (c); an inverting means for reversing every bit of the second output; and a result selecting means for selecting the arithmetic operation from the outputs of said first means and said inverting means.

Claim 6

A floating point processor as set forth in claim 3 which further comprises "carry for rounding" generation means for outputting a carry signal generated at a reference digital position when the rounding is performed at a predetermined digit, said carry signal indicating a carry obtained from the first fraction, part of the second fraction and data obtained at a guard bit, a round bit and a sticky bit by making the weight of bit of the first floating point number equal to that of corresponding bit of the second floating point number, said result selecting means selecting one of the outputs of said carry generation and propagation producing means and said inverting means on the basis of the output of said "carry for rounding" generating means, a signal indicating one of the addition and the subtraction, the overflows and most significant bits in the outputs of said carry generation and propagation producing means.

Claim 7

A floating point processor responsive to input signals representing floating point numbers for performing floating point arithmetic operations on the floating point numbers represented by the input signals, comprising: a first arithmetic means for linearly combining first and second signal values respectively representing first and second fractions of first and second floating point numbers, the first fraction having an exponent larger than the exponent of the other floating point number, said first arithmetic means shifting a second fraction of a second floating point number to cause the weight of corresponding bits to equal that of the first floating point number and the exponent to be less than that of the first floating point number and for deriving a first output signal representing the result of the linear combining of the first and second signal values; a second arithmetic means for performing the same linear combining operation as said first arithmetic means performs on the first fraction and the sum of the second fraction and "1" and for deriving a second output signal representing the result of the linear combining by the second arithmetic means; an inverting means for reversing every bit of the second output signal; and a result selecting means for selecting the arithmetic operation from the output signals of said first and second arithmetic means and said inverting means.

Claim 8

A floating point processor responsive to input signals representing floating point numbers for performing floating point arithmetic operations on the floating point numbers represented by the input signals, comprising: a first arithmetic means for linearly combining first and second signal values respectively representing first and second fractions of first and second floating point numbers, the first fraction having an exponent larger than the exponent of the other floating point number, said first arithmetic means shifting a second fraction of a second floating point number to cause the weight of corresponding bits to equal that of the first floating point number and the exponent to be less than that of the first floating point number and for deriving a first output signal representing the result of the linear combining of the first and second signal values; a second arithmetic means for performing the same linear combining operation as said first arithmetic means performs on the first fraction and the sum of the second fraction and "1" and for deriving a second output signal representing the result of the linear combining by the second arithmetic means; an inverting means for reversing every bit of the second output signal; and a result selecting means for selecting the arithmetic operation from the output signals of said first and second arithmetic means and said inverting means.

Claim 9

A floating point processor as set forth in claim 5 which further comprises "carry for rounding" generation means for deriving a carry signal, the carry signal being derived at a reference digital position in response to the rounding being performed at a predetermined position in response to the rounding being performed at a predetermined digit, said carry signal indicating a carry obtained from part of the first and second fractions and data obtained at a guard bit, a round bit and a sticky bit by causing the bit weight of the first floating point number to equal that of a corresponding bit of the second floating point number, said result selecting means selecting one of the outputs of said first and second arithmetic means and said inverting means on the basis of the output of said "carry for rounding" generation means, a signal indicating whether the linear combining operation is an addition or a subtraction, the overflows and most significant bits in the outputs of said first and second arithmetic means.

Claim 10

A floating point processor responsive to input signals representing floating point numbers for performing floating point arithmetic operations on floating point numbers represented by the input signals, comprising: a carry generation and propagation producing means for (a) linearly combining first and second fractions of first and second floating point numbers, the first fraction having an exponent which is larger than the exponent of the other floating point number, the second floating point number having a weight of corresponding bits equal to that of the first floating point number and an exponent less than that of the first floating point number, (b) deriving a first output signal representing the result of the linear combining of the first and second fractions (c) performing the same linear combining operation as performed on the first fraction and the sum of the second fraction and "1" and (d) deriving a second output signal representing the result of the operation performed on the first fraction and the sum of the second fraction and "1"; an inverting means for reversing every bit of the second output signal; and a result selecting means for selecting the arithmetic operation from the outputs of said carry generation and propagation producing means and said inverting means.

Claim 11

A floating point processor responsive to input signals representing floating point numbers for performing floating point arithmetic operations on floating point numbers represented by the input signals, comprising: a carry generation and propagation producing means for (a) linearly combining first and second fractions of first and second floating point numbers, the first fraction having an exponent which is larger than the exponent of the other floating point number, the second floating point number having a weight of corresponding bits equal to that of the first floating point number and an exponent less than that of the first floating point number, (b) deriving a first output signal representing the result of the linear combining of the first and second fractions (c) performing the same linear combining operation as performed on the first fraction and the sum of the second fraction and "1" and (d) deriving a second output signal representing the result of the operation performed on the first fraction and the sum of the second fraction and "1"; an inverting means for reversing every bit of the second output signal; and a result selecting means for selecting the arithmetic operation from the outputs of said carry generation and propagation producing means and said inverting means.

Claim 12

A floating point processor as set forth in claim 7 which further comprises "carry for rounding" generation means for deriving a carry signal, the carry signal being derived at a reference digital position responsive to the rounding being performed at a predetermined digit, said carry signal indicating a carry obtained from the first fraction, part of the second fraction and data obtained at a guard bit, a round bit and a sticky bit by causing the bit weight of the first floating point number to equal that of a corresponding bit of the second floating point number, said result selecting means selecting one of the outputs of said carry generation and propagation producing means and said inverting means on the basis of the output of said "carry for rounding" generation means, a signal indicating whether the linear combining operation is an addition or a subtraction, the overflows and most significant bits in the outputs of said carry generation and propagation producing means.