Dual output adder and method of addition for concurrently forming the differences a{31 b and b{31 a

Claim 2

A binary carry propagate adder for forming the algebraic sums of operands A and B comprising, first means for generating a +1 constant, second means for forming propagate, generate, carry, and halfsum signals from said +1 constant, from the operand A and from the one''s complement, B'', of the operand B, third means responsive to said signals to form the initial sum A+B'', fourth means responsive to said signals to form the sum A+B''+1 equal to the difference A-B, and fifth means operating concurrently with said fourth means for forming the one''s complement, (A+B'')'', of said initial sum A+B'' to form the difference B-A whereby the differences A-B and B-A are concurrently formed.

Claim 3

A data processing system including apparatus for storing operands A and B, said system including a binary carry propagate adder for forming the algebraic sums of operands A and B comprising, first means for generating a +1 constant, second means for forming propagate, generate, carry, and half-sum signals from said +1 constant, from the operand A and from the one''s complement, B'', of the operand B, third means responsive to said signals to form the initial sum A+B'', fourth means responsive to said signals to form the sum A+B''+1 equal to the difference A-B, and fifth means operating concurrently with said fourth means for forming the one''s complement, (A+B'')'', of said initial sum A+B'' to form the difference B-A whereby the differences A-B and B-A are concurrently formed, and said system including a comparator means for determining which of the operands A and B is greater, and means responsive to said comparator means for selecting the differences A-B if A is greater and selecting the difference B-A if B is greater.

Claim 4

A data processing system including apparatus for storing operands A and B, said system including a binary carry propagate adder for forming the algebraic sums of operands A and B comprising, first means for generating a +1 constant, second means for forming propagate, generate, carry, and half-sum signals from said +1 constant, from the operand A and from the one''s complement, B'', of the operand B, third means responsive to said signals to form the initial sum A+B'', fourth means responsive to said signals to form the sum A+B''+1 equal to the difference A-B, and fifth means operating concurrently with said fourth means for forming the one''s complement, (A+B'')'', of said initial sum A+B'' to form the difference B-A whereby the differences A-B and B-A are concurrently formed, and said system including a comparator means for determining which of the operands A and B is greater, and means responsive to said comparator means for selecting the differences A-B if A is greater and selecting the difference B-A if B is greater.

Claim 5

A data processing system, including apparatus for storing operands A and B and for providing iNput signals representing the operand A and for providing input signals representing the one''s complement, B'', of the operand B, said system including an adder comprising means for phase-splitting said input signals to form two-phase input signals, means responsive to said two phase input signals for generating bit generate, bit propagate, group generate, and group propagate signals, means for generating two''s complement carry signals, means responsive to said group propagate and said group generate signals and responsive to said two''s complement carry signals to form complemented group carry signals, means responsive to said group propagate and said group generate signals to generate uncomplemented group carry signals, means responsive to said bit generate and bit propagate signals for generating half sum signals, means responsive to said half-sum signals and said complemented and uncomplemented group carry signals to form first sum signals representing the difference A-B, means responsive to said half-sum signals and said uncomplemented group carry signals to form initial sum signals, means for one''s complementing said initial sum signals to form second sum signals representing the difference B-A.

Claim 6

A data processing system, including apparatus for storing operands A and B and for providing iNput signals representing the operand A and for providing input signals representing the one''s complement, B'', of the operand B, said system including an adder comprising means for phase-splitting said input signals to form two-phase input signals, means responsive to said two phase input signals for generating bit generate, bit propagate, group generate, and group propagate signals, means for generating two''s complement carry signals, means responsive to said group propagate and said group generate signals and responsive to said two''s complement carry signals to form complemented group carry signals, means responsive to said group propagate and said group generate signals to generate uncomplemented group carry signals, means responsive to said bit generate and bit propagate signals for generating half sum signals, means responsive to said half-sum signals and said complemented and uncomplemented group carry signals to form first sum signals representing the difference A-B, means responsive to said half-sum signals and said uncomplemented group carry signals to form initial sum signals, means for one''s complementing said initial sum signals to form second sum signals representing the difference B-A.

Claim 7

The system of claim 3 further including, a comparator for comparing the operands A and B to determine which is greater, and means responsive to said comparator for selecting said first sum signals if A is greater than B and selecting said second sum signals if B is greater than A.

Claim 8

The system of claim 4 further including means responsive to said comparator for selecting said first sum signals if A equals B.

Claim 9

The system of claim 3 further including an instruction unit, storage units for storing floating point instructions, and control means for fetching the floating point instructions to the instruction unit and operands A and B to the apparatus for storing operands A and B, said operands A and B including sign, mantissa, and exponent portions, said system including means for shifting the mantissa portions of said operands A and B into alignment in response to the difference A-B if A is greater than B or in response to the difference B-A if B is greater than A.

Claim 10

A data processing system, including apparatus for storing operands A and B and for providing input signals representing the operand A and for providing input signals representing the one''s complement, B'', of the operand B, said system including an adder comprising, a firt level of logic including means for phase-splitting said input signals to form two phase input signals, a second level of logic including means responsive to said two phase input signals for generating bit generate, bit propagate, group generate, and group propagate signals, and including means for generating two''s complement carry signals, a third level of logic including means responsive to said group propagate and said group generate signals and responsive to said two''s complement carry signals to form complemented group carry signals, including means responsive to said group propagate and said group generate signals to generate uncomplemented group carry signals, and including means responsive to said bit generate and bit propagate signals for generating half-sum signals, a fourth level of logic including means responsive to said half-sum signals and said complemented and uncomplemented group carry signals to form first sum signals representing the difference A-B, and including means responsive to said halfsum signals and said uncomplemented group carry signals to form initial sum signals, and a fifth level of logic including means for one''s complementing said initial sum signals to form second sum signals representing the difference B-A and including means for powering said first sum signals representing the difference A-B.

Claim 11

A data processing system, including apparatus for storing operands A and B and for providing input signals representing the operand A and for providing input signals representing the one''s complement, B'', of the operand B, said system including an adder comprising, a firt level of logic including means for phase-splitting said input signals to form two phase input signals, a second level of logic including means responsive to said two phase input signals for generating bit generate, bit propagate, group generate, and group propagate signals, and including means for generating two''s complement carry signals, a third level of logic including means responsive to said group propagate and said group generate signals and responsive to said two''s complement carry signals to form complemented group carry signals, including means responsive to said group propagate and said group generate signals to generate uncomplemented group carry signals, and including means responsive to said bit generate and bit propagate signals for generating half-sum signals, a fourth level of logic including means responsive to said half-sum signals and said complemented and uncomplemented group carry signals to form first sum signals representing the difference A-B, and including means responsive to said halfsum signals and said uncomplemented group carry signals to form initial sum signals, and a fifth level of logic including means for one''s complementing said initial sum signals to form second sum signals representing the difference B-A and including means for powering said first sum signals representing the difference A-B.

Claim 12

The sYstem of claim 7 further including means for ingating said operand A and the inverse B'' of operand B into said first level of logic where A and B'' each include four bits represented by the input signals a4, . . . , a7 and b4, . . . , b7, respectively.

Claim 13

The system of claim 7 wherein said logic levels include a plurality of NOR/OR gates having outputs connected in common to form logical OR functions.

Claim 14

In a data processing system which stores data and instructions and has a plurality of units for executing the instructions including a carry propagate adder operated in accordance with algorithms for forming the algebraic sums of operands A and B, the improvement comprising the sequential steps of, generating, in response to input signals representing operand A and the one''s complement, B'', of operand B, bit propagate, bit generate, group propagate, and group generate signals, and generating carry signals, generating, in response to said bit propagate and bit generate signals, half sum signals and concurrently generating, in response to said group propagate, group generate and carry signals, uncomplemented group carry signals and complemented group carry signals, logically combining said complemented and uncomplemented group carry signals and said half sum signals to form first sum signals representing the difference A-B and concurrently logically combining said uncomplemented group carry signals and said half sum signals to form initial sum signals, and one''s complementing said initial sum signals to form second sum signals representing the difference B-A.

Claim 15

In a data processing system which stores data and instructions and has a plurality of units for executing the instructions including a carry propagate adder operated in accordance with algorithms for forming the algebraic sums of operands A and B, the improvement comprising the sequential steps of, generating, in response to input signals representing operand A and the one''s complement, B'', of operand B, bit propagate, bit generate, group propagate, and group generate signals, and generating carry signals, generating, in response to said bit propagate and bit generate signals, half sum signals and concurrently generating, in response to said group propagate, group generate and carry signals, uncomplemented group carry signals and complemented group carry signals, logically combining said complemented and uncomplemented group carry signals and said half sum signals to form first sum signals representing the difference A-B and concurrently logically combining said uncomplemented group carry signals and said half sum signals to form initial sum signals, and one''s complementing said initial sum signals to form second sum signals representing the difference B-A.

Claim 16

The method of claim 10 further including the steps of, comparing the operands A and B to determine which is greater, selecting the difference A-B if A is greater than B and selecting the difference B-A if B is greater than A.