Parallel binary carry look-ahead adder system

Claim 1

In a multiple bit binary parallel adder system for adding together the bits of two binary words, said system containing a plurality of multiple bit group parallel adders and wherein the output carry from the highest order bit of each group adder constitutes the input carry for the lowest order bit of the nexthigher order group adder, the improvement wherein at least one of said group adders comprises: a plurality of full adders Vi, where i is a number which represents the bit location in the words, each of said full adder Vi having inPuts Xi, Yi for summands of the same designation, an input Wi for the output carry Zi 1 of the next-lower order bit, an output Si for the sum of the bits and output Zi for the output carry; a plurality of logic stages connected to the summand inputs for forming the values Gi Xi. Yi, Pi Xi + Yi, and Gi, Pi for the corresponding complementary values; and, logic circuit means for rapidly forming the output carry of said at least one group adder by compiling values corresponding to all of the input values to said at least one group adder, while all of the other carries within said at least one group adder are formed as propagated carriers, said logic circuit means including a plurality of logic circuits L Mu where Mu 1,2, . . . m, each of said logic circuits having at least one first input A1 Mu , A2 Mu . . . , at least one second input B1 Mu , B2 Mu . . . , outputs C Mu and C Mu , and means interconnecting said first and second inputs and said outputs for establishing the following relationships, C Mu A1 Mu + A2 Mu + . . . +B1 Mu + B2 Mu + . . . C Mu A1 Mu + A2 Mu + . . . (B1 Mu + B2 Mu . . .).