US4888722A
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US
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Parallel arithmetic-logic unit for as an element of digital signal processor
Assignee: GENERAL DAACOMM Inc
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Filing: 1987-07-02
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Granted: 1989-12-19
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Expires: 2007-07-02
Abstract
Abstract A parallel arithmetic-logic unit (PALU) controlled by a microinstruction sequencer and capable of executing conditional operations in a single pass is disclosed. The PALU generally comprises first and second registers for storing data, a comparator for continually comparing the values in the registers, and an arithmetic-logic core connected to the registers for performing arithmetic, logical and data move operations on the data in the registers. The comparator is preferably an unsigned magnitude comparator which outputs flags indicative of the relative status of the values in the registers. The flags are read by a microinstruction sequencer which then uses the flag information to determine what operation the arithmetic-logic core is to conduct. Preferably, a shifter is also provided between one of the registers and the arithmetic-logic core.
Inventors
- 👤 Charles P. Boreland
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 19:37
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/57; G06F7/575
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
152 words
A parallel arithmetic-logic unit controlled by a microinstruction sequencer, comprising: (a) a first register for storing data; (b) a second register for storing data; (c) a comparator means, including means for setting at least one flag, said comparator means being connected to said first and second registers, for continually comparing the values of the data in said first and second registers and causing said flag setting means to set at least one flag depending on the results of the comparison, wherein said at least one flag is read by said microinstruction sequencer; and (d) an arithmetic-logic core means connected to said first and second registers for performing at least one of an arithmetic, logic and data move operation on at least the data in one of said first and second registers based on instructions from said microinstruction sequencer which were at least partially formed in response to said at least one flag.
Claim 2
Dependent Claim
152 words
A parallel arithmetic-logic unit controlled by a microinstruction sequencer, comprising: (a) a first register for storing data; (b) a second register for storing data; (c) a comparator means, including means for setting at least one flag, said comparator means being connected to said first and second registers, for continually comparing the values of the data in said first and second registers and causing said flag setting means to set at least one flag depending on the results of the comparison, wherein said at least one flag is read by said microinstruction sequencer; and (d) an arithmetic-logic core means connected to said first and second registers for performing at least one of an arithmetic, logic and data move operation on at least the data in one of said first and second registers based on instructions from said microinstruction sequencer which were at least partially formed in response to said at least one flag.
Claim 3
Dependent Claim
31 words
A parallel arithmetic-logic unit according to claim 1, further comprising: (e) at least one shifter connected between at least one of said first and second registers and said arithmetic-logic core means.
Claim 4
Dependent Claim
44 words
A parallel arithmetic-logic unit according to claim 2, wherein: each of said at least one shifter reads the data of its associated register, shifts the data in response to instructions of said microinstruction sequencer, and supplies the shifted data to said arithmetic-logic core means.
Claim 5
Dependent Claim
19 words
A parallel arithmetic-logic unit according to claim 2, wherein: said at least one shifter comprises an unsigned magnitude shifter.
Claim 6
Dependent Claim
57 words
A parallel arithmetic-logic unit according to claim 1, wherein: said arithmetic-logic core performs the subtracting the value in said first register from the value in said second register, subtracting the value in said second register from the value in said first register, and adding the value in said first register to the value in said second register.
Claim 7
Dependent Claim
61 words
A parallel arithmetic-logic unit according to claim 5, wherein: said arithmetic-logic core further performs the incrementing and decrementing the value of at least one of said first and second registers, negating the value of at least one of said first and second registers, and providing an absolute value of a value in at least one of said first and second registers.
Claim 8
Dependent Claim
52 words
A parallel arithmetic-logic unit according to claim 6, wherein: said arithmetic-logic core further performs the converting a two's complement value in one of said first and second registers to a signed magnitude value, and converting a signed magnitude value is one of said first and second registers into a two's complement value.
Claim 9
Dependent Claim
59 words
A parallel arithmetic-logic unit according to claim 6, wherein: said arithmetic-logic core further performs the conducting a logical exclusive OR function on the values in said first and second registers, conducting a logical OR function on the values in said first and second registers, and conducting a logical AND function on the values in said first and second registers.
Claim 10
Dependent Claim
142 words
A parallel arithmetic-logic unit according to claim 5, further comprising: (e) at least one shifter connected between at least one of said first and second registers and said arithmetic-logic core means, wherein each of said at least one shifter reads the data of its associated register, shifts the data in response to instructions of said microinstruction sequencer, and supplies the shifted data to said arithmetic-logic core means, and wherein said arithmetic-logic core performs the shifting the bits of the value in said first register and subtracting the shifted value from the value in said second register, shifting the bits of the value in said first register an d subtracting the value in said second register from the shifted value, and shifting the bits of the value in said first register and adding the shifted value to the value in said second register.
Claim 11
Dependent Claim
51 words
A parallel arithmetic-lgoic unit according to claim 1 wherein: said arithmetic-logic core performs the converting a two's complement value in one of said first and second registers to a signed magnitude value, and converting a signed magnitude value is one of said first and second registers into a two's complement value.
Claim 12
Dependent Claim
70 words
A parallel arithmetic-logic unit according to claim 1, wherein: said at least one flag comprises at least two flags for indicating when the value in said first register is greater than the value in said second register, when the value in said first register is equal to the value in said second register, and when the value in said first register is less than the value in said second register.
Claim 13
Dependent Claim
59 words
A parallel arithmetic-logic unit according to claim 11 wherein: said at least two flags comprises three flags for also indicating when the value in said first register is greater than or equal to the value in said second register, and when the value in said first register is less than or equal to the value in said second register.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-12-18 | 1993-06-19 | 1993-12-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-12-18 | 1997-06-19 | 1997-12-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-12-18 | 2001-06-19 | 2001-12-19 | $7700.00 | Window Closed / Lapsed |