US4649508A
Expired / Lapsed
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Floating-point arithmetic operation system
Assignee: Toshiba Corp
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Filing: 1983-10-27
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Granted: 1987-03-10
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Expires: 2003-10-27
Abstract
Abstract In a floating-point arithmetic operation system performing an arithmetic operation on two given operands X, Y and providing the result Z of the arithmetic operation, the operands X and Y are each classified according to their attributes; and, at least part of the bits of the operand X, at least part of the bits of the operand Y or a predetermined set of bits are adopted as at least part of the result Z of the operation when the results of the classifications are one of predetermined combinations.
Inventors
- 👤 Akira Kanuma
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 07:27
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/483
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
183 words
A floating-point arithmetic operation system for performing an arithmetic operation on two given operands X, Y and providing the result Z of the arithmetic operation, comprising: an X classification circuit receiving at least part of the bits representing the operand X to classify the operand X based only on said received operand X bits and producing at least one corresponding X class signal indicative of the result of the classification; a Y classification circuit receiving at least part of the bits representing the operand Y to classify the operand Y based only on said received operand Y bits and producing at least one corresponding Y class signal indicative of the result of the classification; and adopting means responsive to the X class signal, and Y class signal for adopting at least part of the bits of the corresponding operand X, at least part of the bits of the corresponding operand Y or a predetermined set of bits, as at least part of the result of Z of the operation when the X class signal and the Y class signal are in predetermined categories.
Claim 2
Dependent Claim
183 words
A floating-point arithmetic operation system for performing an arithmetic operation on two given operands X, Y and providing the result Z of the arithmetic operation, comprising: an X classification circuit receiving at least part of the bits representing the operand X to classify the operand X based only on said received operand X bits and producing at least one corresponding X class signal indicative of the result of the classification; a Y classification circuit receiving at least part of the bits representing the operand Y to classify the operand Y based only on said received operand Y bits and producing at least one corresponding Y class signal indicative of the result of the classification; and adopting means responsive to the X class signal, and Y class signal for adopting at least part of the bits of the corresponding operand X, at least part of the bits of the corresponding operand Y or a predetermined set of bits, as at least part of the result of Z of the operation when the X class signal and the Y class signal are in predetermined categories.
Claim 3
Dependent Claim
67 words
A system of claim 1, wherein said adopting means comprises: a control logic circuit responsive to the X class signal and the Y class signal for producing a set of control signals; and selecting means receiving, as the inputs, the corresponding operand X, the corresponding operand Y and at least one predetermined set of bits and selecting one of the inputs in accordance with the control signals.
Claim 4
Dependent Claim
39 words
A system of claim 2, wherein said control logic circuit also receives a command signal specifying the kind of arithmetic operation to be performed, and is also dependent on the command signal for producing said set of control signals.
Claim 5
Dependent Claim
115 words
A signal of claim 1, further comprising: a floating-point arithmetic operation unit performing an arithmetic operation on the operands X and Y; and a control circuit responsive to the corresponding X class signal and the corresponding Y class signal for producing a set of control signals; wherein said adopting means comprises selecting means having an output and having inputs receiving the result of the arithmetic operation performed by said floating-point arithmetic operation unit, at least part of the bits of the operand X, at least part of the bits of the operand Y, and a predetermined set of bits and selectively providing one of the inputs to the output in accordance with the control signals.
Claim 6
Dependent Claim
56 words
A system of claim 4, wherein said floating-point arithmetic operation unit comprises a floating-point multiplication unit comprising a mantissa processor performing multiplication on the mantissas of the operands X and Y and normalization where necessary and an exponent processor performing addition of the exponents of the operands X and Y, and adjustment attendant on the normalization.
Claim 7
Dependent Claim
130 words
A system of claim 1, further comprising: a floating-point arithmetic operation unit performing an arithmetic operation on the operands X and Y when the corresponding X class signal and Y class signal do not fall into said predetermined categories; and a control circuit responsive to the X class signal and the Y class signal for producing a set of control signals wherein said adopting means comprises selecting means having an output and having inputs receiving the result of the arithmetic operation performed by said floating-point arithmetic operation unit, at least part of the bits of the operand X, at least part of the bits of the operand Y, and a predetermined set of bits and selectively providing one of the inputs to the output in accordance with the control signals.
Claim 8
Dependent Claim
56 words
A system of claim 6, wherein said floating-point arithmetic operation unit comprises a floating-point multiplication unit comprising a mantissa processor performing multiplication on the mantissas of the operands X and Y and normalization where necessary and an exponent processor performing addition of the exponents of the operands X and Y, and adjustment attendant on the normalization.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-03-09 | 1990-09-08 | 1991-03-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-03-09 | 1994-09-08 | 1995-03-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-03-09 | 1998-09-08 | 1999-03-10 | $7700.00 | Window Closed / Lapsed |