US4608660A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data processing system with condition data setting function
Assignee: Toshiba Corp
•
Filing: 1984-01-25
•
Granted: 1986-08-26
•
Expires: 2004-01-25
Abstract
Abstract A data processing system with a condition data setting function is provided. In the system, a microprogram memory designed stores a plurality of specific subtraction micro-instructions for obtaining condition data consisting of a combination of bits respectively representing the sign of the results of each of a plurality of substraction operations. A micro-instruction read out from said microprogram memory is loaded into a micro-instruction register. An arithmetic and logic section performs an arithmetic operation, in accordance with the specific subtraction micro-instructions loaded in said micro-instruction register, and outputs status data including a carry flag and a sign flag. A multiplexer selects the carry flag or sign flag, in accordance with the first specific bit of the specific subtraction micro-instruction loaded in said micro-instruction register. The flag thus selected is input to a serial-to-parallel shift register, as one of the bits of said condition data, under control of the second specific bit of the specific subtraction micro-instruction. The condition data is a direction discrimination code used in a Bresenham DDA and is used as an index for determining which processing operation is to be performed next.
Inventors
- 👤 Kouki Hasebe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 02:46
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/20
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
171 words
A data processing system with a condition data setting function, comprising: a microprogram memory for storing microprograms consisting of micro-instructions including a plurality of specific subtraction micro-instructions for obtaining condition data consisting of a combination of bits respectively representing the sign of the results of each of a plurality of subtraction operations; a micro-instruction register into which a micro-instruction read out from said microprogram memory is loaded; an arithmetic and logic section which performs an arithmetic operation, in accordance with the specific subraction micro-instruction loaded in said micro-instruction register, and which outputs status data including a carry flag and a sign flag; and a multiplexer for selecting one of said carry flag and sign flag, in response to a specific bit of the specific subtraction micro-instruction received from said micro-instruction register; and serial-to-parallel converting means for receiving the output from said multiplexer, as one of the bits of said condition data, and shifting the data already stored, thereby holding the condition data which has been obtained from the specific subtraction micro-instructions.
Claim 2
Dependent Claim
171 words
A data processing system with a condition data setting function, comprising: a microprogram memory for storing microprograms consisting of micro-instructions including a plurality of specific subtraction micro-instructions for obtaining condition data consisting of a combination of bits respectively representing the sign of the results of each of a plurality of subtraction operations; a micro-instruction register into which a micro-instruction read out from said microprogram memory is loaded; an arithmetic and logic section which performs an arithmetic operation, in accordance with the specific subraction micro-instruction loaded in said micro-instruction register, and which outputs status data including a carry flag and a sign flag; and a multiplexer for selecting one of said carry flag and sign flag, in response to a specific bit of the specific subtraction micro-instruction received from said micro-instruction register; and serial-to-parallel converting means for receiving the output from said multiplexer, as one of the bits of said condition data, and shifting the data already stored, thereby holding the condition data which has been obtained from the specific subtraction micro-instructions.
Claim 3
Dependent Claim
43 words
A system according to claim 1, wherein said multiplexer selects the carry flag, in accordance with the first specific bit, when the data within said arithmetic and logic section, which is specified by the specific subtraction micro-instruction, is numerical data without a sign.
Claim 4
Dependent Claim
43 words
A system according to claim 1, wherein said multiplexer selects the sign flag, in accordance with the first specific bit, when the data within said arithmetic and logic section, which is specified by the specific subtraction micro-instruction, is numerical data with a sign.
Claim 5
Dependent Claim
26 words
A system according to claim 1, wherein the specific subtraction micro-instruction includes a second specific bit for controlling the shift operation of said serial-to-parallel converting means.
Claim 6
Dependent Claim
41 words
A system according to claim 1, wherein the condition data comprises a 3-bit direction discrimination code for a line connecting a start point P 0 (x 0 ,y 0 ) and an end point P 1 (x 1 ,y 1 ).
Claim 7
Dependent Claim
105 words
A system according to claim 5, wherein the plurality of specific subtraction micro-instructions are three micro-instructions consisting of a first micro-instruction for obtaining a difference Δy between a y-coordinate y 1 of the end point P 1 and a y-coordinate y 0 of the start point P 0 , a second micro-instruction for obtaining a difference Δx between an x-coordinate x 1 of the end point P 1 and an x-coordinate x 0 of the start point P 0 , and a third micro-instruction for obtaining a difference S between an absolute value |Δx| of difference Δx and an absolute value |Δy| of difference Δy.
Claim 8
Dependent Claim
31 words
A system according to claim 6, wherein the data output by said serial-to-parallel converting means when all of the first to third micro-instructions have been executed represents the direction discrimination code.
Claim 9
Dependent Claim
16 words
A system according to claim 7, wherein said serial-to-parallel converting means comprises a serial-to-parallel shift register.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-08-25 | 1990-02-24 | 1990-08-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-08-25 | 1994-02-24 | 1994-08-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-08-25 | 1998-02-24 | 1998-08-26 | $7700.00 | Window Closed / Lapsed |