Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
122 words
Apparatus for performing floating point addition and subtraction operations, said apparatus comprising: addition means for performing floating point effective addition; and subtraction means for performing floating point effective subtraction, said subtraction means including: first subtraction means responsive to initial operand exponent argument signals for identifying correct final fraction signals; second subtraction means responsive to a subset of said initial operand exponent argument signals for identifying possible final fraction signals; third subtraction means responsive to said second subtraction means and to said initial operand fraction signals for providing a first possible final fraction signals; and selection means responsive to said first subtraction means for selecting said correct final fraction signals from said first possible final fraction signals and said initial operand fraction signals.
Claim 2
Dependent Claim
122 words
Apparatus for performing floating point addition and subtraction operations, said apparatus comprising: addition means for performing floating point effective addition; and subtraction means for performing floating point effective subtraction, said subtraction means including: first subtraction means responsive to initial operand exponent argument signals for identifying correct final fraction signals; second subtraction means responsive to a subset of said initial operand exponent argument signals for identifying possible final fraction signals; third subtraction means responsive to said second subtraction means and to said initial operand fraction signals for providing a first possible final fraction signals; and selection means responsive to said first subtraction means for selecting said correct final fraction signals from said first possible final fraction signals and said initial operand fraction signals.
Claim 3
Dependent Claim
60 words
The apparatus for performing floating point addition and subtraction operations of claim 1 wherein said third subtraction means has combining means for providing a combined operand fraction from two initial operand fraction signals, wherein a first of said initial operand fraction signals is shifted by an amount determined by said second subtraction means prior to combining in said combining means.
Claim 4
Dependent Claim
25 words
The apparatus for performing floating point addition and subtraction operations of claim 2 wherein said second subtraction is a portion of said first subtraction means.
Claim 5
Dependent Claim
33 words
The apparatus for performing floating point addition and subtraction of claim 3 wherein said operand exponential argument signal subset can store a quantity greater than the number of positions representing an operand fraction.
Claim 6
Dependent Claim
23 words
The apparatus for performing floating point addition and subtraction operations of claim 1 wherein said first and second subtraction means operate in parallel.
Claim 7
Dependent Claim
38 words
The apparatus for performing floating point addition and subtraction operations of claim 1 wherein said second and said third subtraction means determines said possible final fraction signals requiring calculation in parallel with operation of said first subtraction means.
Claim 8
Dependent Claim
35 words
The apparatus for performing floating point addition and subtraction operations of claim 1 further comprising operation means responsive to operand fraction signs for selecting a one of an effective addition and an effective subtraction operation.
Claim 9
Independent Claim
84 words
The method of performing an effective subtraction operation for floating point operands, said method comprising the steps of: determining a first difference between two operand exponent argument signals, said first difference determining how two operand fractions are to be combined; determining a second difference between a subset of said two operand exponent signals, said second difference defining a possible combination of said two operand fractions; and selecting a correct final fraction result from a one of said possible operand combination and said operand fractions.
Claim 10
Independent Claim
84 words
The method of performing an effective subtraction operation for floating point operands, said method comprising the steps of: determining a first difference between two operand exponent argument signals, said first difference determining how two operand fractions are to be combined; determining a second difference between a subset of said two operand exponent signals, said second difference defining a possible combination of said two operand fractions; and selecting a correct final fraction result from a one of said possible operand combination and said operand fractions.
Claim 11
Dependent Claim
31 words
The method of performing an effective subtraction operation of claim 8 further comprising the step of initiating calculation of said possible operand combination in parallel with said determining said first difference.
Claim 12
Dependent Claim
47 words
The method of performing an effective subtraction operation of claim 8 further comprising the step of selecting said operand exponent argument subset of a plurality of least significant bits, said plurality of least significant bits representing a quantity larger than the number of operand fraction bit positions.
Claim 13
Dependent Claim
24 words
The method of performing an effective subtraction operation of claim 8 further comprising the step of controlling said selecting step by said first difference.
Claim 14
Dependent Claim
35 words
The method of performing an effective subtraction operation of claim 8 further comprising the steps of unsing said second difference to control shifting of said operand fractions, and applying said operands to a subtraction circuit.
Claim 15
Dependent Claim
78 words
Apparatus for implementing an effective subtraction operation for floating point operands, said apparatus comprising: first subtraction means for determining a first difference between operand exponent argument signals; second subtraction means for determining a second difference between a selected subset of said operand exponent argument signals; third subtraction means responsive to said second difference for determining a third difference between operand fractions applied thereto; and selection means for selecting a one of said third difference and said operand fractions.
Claim 16
Dependent Claim
78 words
Apparatus for implementing an effective subtraction operation for floating point operands, said apparatus comprising: first subtraction means for determining a first difference between operand exponent argument signals; second subtraction means for determining a second difference between a selected subset of said operand exponent argument signals; third subtraction means responsive to said second difference for determining a third difference between operand fractions applied thereto; and selection means for selecting a one of said third difference and said operand fractions.
Claim 17
Dependent Claim
39 words
The apparatus for implementing an effective subtraction operation of claim 13 further comprising shifting means, wherein said operand fractions applied to said third subtractin means are shifted by said shifting means by an amount determined by said second difference.
Claim 18
Dependent Claim
21 words
The apparatus for implementing an effective subtraction operation of claim 14 wherein said selection means is responsive to said first difference.
Claim 19
Dependent Claim
48 words
The apparatus for implementing an effective subtraction operation of claim 15 wherein said subset includes a plurality of least significant signals of said operand exponent arguments, said plurality being at least large enough to represent a quantity greater than the number of bit positions of said operand fractions.
Claim 20
Dependent Claim
48 words
The apparatus for implementing an effective subtraction operation of claim 16 wherein said shifting means includes a first shifting means for shifting said operand fractions by 0 and by 1 bit position, and a second shifting means for shifting said operand fractions by greater than one bit position.