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US5117388A
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Serial input/output semiconductor memory
Assignee: Fujitsu VLSI Ltd
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Filing: 1991-09-18
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Granted: 1992-05-26
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Expires: 2011-09-18
Abstract
Abstract A semiconductor memory comprises a memory cell array which includes a plurality of memory cells respectively connected to one of a plurality of word lines and to one of a plurality of bit lines, a serial data register which includes a number of bit cells corresponding to one word of the memory cell array, a decoder for decoding an address signal and for successively making an access to each bit cell of the serial data register based on a decoded result, a register group comprising m+1 shift registers in correspondence with each digit of the address signal, where each of the shift registers comprise n registers which are connected to form a loop and m and n are integers satisfying m≧0 and n>2, a shift circuit for shifting a content of one of the shift registers corresponding to a least significant digit of the address signal in response to a clock signal, and a transfer circuit for transferring a carry information which is received from a first arbitrary one of the shift registers to a second arbitrary one of the shift registers. The first arbitrary shift register corresponds to an ith most significant digit of the address signal, the second arbitrary shift register corresponds to a (i+1)th most significant digit of the address signal, and output signals of the shift registers are used as the address signal.
Inventors
- 👤 Masao Nakano
- 👤 Satoru Kawamoto
- 👤 Akihiko Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 14:26
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C7/00; G11C7/10; G11C7/1075; G11C19/00
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
176 words
A semiconductor memory which outputs data serially, said semiconductor memory comprising: a serial data register for storing a plurality of bits of data; a first shift register having a plurality of first registers with input and output ends thereof which are coupled in a loop, said first shift register shifting a content among said plurality of first registers in response to a clock signal; a second shift register having a plurality of second registers with input and output ends thereof which are coupled in a loop, said second shift register shifting a content among said plurality of second registers in response to a shift clock signal which is obtained from a most significant bit from one of said plurality of first registers of said first shift register; and a decoder which receives as an internal address a plurality of bits of data within said first and second shift registers, said decoder being coupled to a serial data register and designating a bit to be output out of he plurality of bits based on the internal address.
Claim 2
Dependent Claim
176 words
A semiconductor memory which outputs data serially, said semiconductor memory comprising: a serial data register for storing a plurality of bits of data; a first shift register having a plurality of first registers with input and output ends thereof which are coupled in a loop, said first shift register shifting a content among said plurality of first registers in response to a clock signal; a second shift register having a plurality of second registers with input and output ends thereof which are coupled in a loop, said second shift register shifting a content among said plurality of second registers in response to a shift clock signal which is obtained from a most significant bit from one of said plurality of first registers of said first shift register; and a decoder which receives as an internal address a plurality of bits of data within said first and second shift registers, said decoder being coupled to a serial data register and designating a bit to be output out of he plurality of bits based on the internal address.
Claim 3
Dependent Claim
107 words
The semiconductor memory as claimed in claim 1, which further comprises: a third shift register which has a plurality of third registers with input and output ends thereof which are coupled in a loop, said third shift register shifting a content among said plurality of third registers in response to a shift clock signal which is obtained from a most significant bit from one of said second registers, said decoder receiving as an internal address a plurality of bits of data within said first, second and third shift registers and designating a bit to be output out of the plurality of bits based on the internal address.
Claim 4
Dependent Claim
99 words
The semiconductor memory as claimed in claim 1 which further comprises a plurality of third shift registers each having input and output ends thereof which are coupled, each of said third shift registers shifting a content thereof in response to a shift clock signal which is obtained from a most significant bit of a shift register in a preceding stage, said decoder receiving as an internal address a plurality of bits of data within said first, second and third shift registers and designating a bit to be output out of the plurality of bits based on the internal address.
Claim 5
Dependent Claim
30 words
The semiconductor memory as claimed in claim 1 wherein said first and second shift registers are set with an initial value which is obtained by decoding an external binary address.
Claim 6
Dependent Claim
271 words
A semiconductor memory which outputs data serially, said semiconductor memory comprising: a serial data register for storing a plurality of bits of data; a first shift register having a plurality of first registers with input and output ends thereof which are coupled in a loop, said first shift register shifting a content among the plurality of first registers in response to a clock signal; a second shift register having a plurality of second registers with input and output ends thereof which are coupled in a loop, said second shift register shifting a content among said plurality of second registers in response to a shift clock signal which is obtained from a most significant bit from one of the plurality of first registers of said first shift register; a decoder which receives as an internal address a plurality of bits of data within said first and second shift registers, said decoder being coupled to a serial data register and designating a bit to be output out of the plurality of bits based on the internal address; a random access memory cell array coupled to said serial data register; a row decoder which decodes a row address for making access to said random access memory cell array; and a column decoder which decodes a column address for making access to said random access memory cell array, said column decoder including a first column decoder for predecoding the column address and a second column decoder for decoding an output of said first column decoder, the output of said first column decoder being set in said first and second shift registers as an initial value.
Claim 7
Dependent Claim
271 words
A semiconductor memory which outputs data serially, said semiconductor memory comprising: a serial data register for storing a plurality of bits of data; a first shift register having a plurality of first registers with input and output ends thereof which are coupled in a loop, said first shift register shifting a content among the plurality of first registers in response to a clock signal; a second shift register having a plurality of second registers with input and output ends thereof which are coupled in a loop, said second shift register shifting a content among said plurality of second registers in response to a shift clock signal which is obtained from a most significant bit from one of the plurality of first registers of said first shift register; a decoder which receives as an internal address a plurality of bits of data within said first and second shift registers, said decoder being coupled to a serial data register and designating a bit to be output out of the plurality of bits based on the internal address; a random access memory cell array coupled to said serial data register; a row decoder which decodes a row address for making access to said random access memory cell array; and a column decoder which decodes a column address for making access to said random access memory cell array, said column decoder including a first column decoder for predecoding the column address and a second column decoder for decoding an output of said first column decoder, the output of said first column decoder being set in said first and second shift registers as an initial value.
Claim 8
Dependent Claim
177 words
A semiconductor memory which outputs data serially, said semiconductor memory comprising: a serial data register for storing s M bits of data, where M>3; N shift registers each having input and output ends thereof which are coupled in a loop, where N>1, each of said N shift registers storing 2 M/N bits of data, one of said N shift registers shifting a content thereof internally among 2 M/N bit registers of the one of said N shift registers in response to a clock signal, remaining N-1 shift registers each shifting a content thereon internally among 2 M/N bit registers of each of the remaining N-1 shift registers in response to a shift clock signal which is obtained from a most significant bit of a shift register in a preceding stage; and a decoder which receives as an internal address a plurality of bits of data within said N shift register, said decoder being coupled to said serial data register and designating a bit to be output out of the plurality of bits based on the internal address.
Claim 9
Dependent Claim
177 words
A semiconductor memory which outputs data serially, said semiconductor memory comprising: a serial data register for storing s M bits of data, where M>3; N shift registers each having input and output ends thereof which are coupled in a loop, where N>1, each of said N shift registers storing 2 M/N bits of data, one of said N shift registers shifting a content thereof internally among 2 M/N bit registers of the one of said N shift registers in response to a clock signal, remaining N-1 shift registers each shifting a content thereon internally among 2 M/N bit registers of each of the remaining N-1 shift registers in response to a shift clock signal which is obtained from a most significant bit of a shift register in a preceding stage; and a decoder which receives as an internal address a plurality of bits of data within said N shift register, said decoder being coupled to said serial data register and designating a bit to be output out of the plurality of bits based on the internal address.
Claim 10
Dependent Claim
31 words
The semiconductor memory as claimed in claim 6 wherein each of said N shift registers are set with an initial value which is obtained by decoding an external M/N-bit binary address.
Claim 11
Dependent Claim
224 words
A semiconductor memory comprising: a memory cell array which includes a plurality of memory cells respectively connected to one of a plurality of word lines and to one of a plurality of bit lines; a serial data register which includes a number of bit cells corresponding to one word of said memory cell array; first decoder means for decoding an address signal and for successively making an access to each bit cell of said serial data register based on a decoded result; a register group comprising m+1 shift registers in correspondence with each digit of the address signal, each of said shift registers comprising n registers which are connected to form a loop, where m and n are integers satisfying m≧0 and n>2; shift means for shifting a content of one of said shift registers corresponding to a least significant digit of the address signal in response to a clock signal; and transfer means for transferring a carry information which is received from a first arbitrary one of said shift registers to a second arbitrary one of said shift registers, said first arbitrary shift register corresponding to an with most significant digit of the address signal, said second arbitrary shift register corresponding to a (i+1)th most significant digit of the address signal, output signals of said shift registers being used as said address signal.
Claim 12
Dependent Claim
224 words
A semiconductor memory comprising: a memory cell array which includes a plurality of memory cells respectively connected to one of a plurality of word lines and to one of a plurality of bit lines; a serial data register which includes a number of bit cells corresponding to one word of said memory cell array; first decoder means for decoding an address signal and for successively making an access to each bit cell of said serial data register based on a decoded result; a register group comprising m+1 shift registers in correspondence with each digit of the address signal, each of said shift registers comprising n registers which are connected to form a loop, where m and n are integers satisfying m≧0 and n>2; shift means for shifting a content of one of said shift registers corresponding to a least significant digit of the address signal in response to a clock signal; and transfer means for transferring a carry information which is received from a first arbitrary one of said shift registers to a second arbitrary one of said shift registers, said first arbitrary shift register corresponding to an with most significant digit of the address signal, said second arbitrary shift register corresponding to a (i+1)th most significant digit of the address signal, output signals of said shift registers being used as said address signal.
Claim 13
Dependent Claim
55 words
The semiconductor memory as claimed in claim 8 wherein said register group outputs an (m+1)-digit n-ary signal as said address signal, each of said shift registers outputting a corresponding one of m+1 digits of the n-ary signal, where the m+1 digits are n O , n 1 , . . . , n m .
Claim 14
Dependent Claim
12 words
The semiconductor memory as claimed in claim 9 wherein m=2 and n=8.
Claim 15
Dependent Claim
65 words
The semiconductor memory as claimed in claim 8 wherein said registers comprise n counters for counting the clock signal, a jth counter receiving an output of a (j-1)th counter and outputting an output thereof to a (j+1)th counter, where j=2, 3, . . . , n-1, an nth counter receiving an output of a (n-1)th counter and outputting an output thereof to a first counter.
Claim 16
Dependent Claim
38 words
The semiconductor memory as claimed in claim 8 which further comprises second decoder means for decoding an external address and for making access to a predetermined memory cell within said memory cell array based on a decoded result.
Claim 17
Dependent Claim
56 words
The semiconductor memory as claimed in claim 12 which further comprises first input/output means coupled to said second decoder means for inputting and outputting random data to and from said memory cell array, and second input/output means coupled to said serial data register for inputting and outputting serial data to and from said serial data register.
Claim 18
Dependent Claim
33 words
The semiconductor memory as claimed in claim 8 which further comprises a redundant address switching circuit for activating a redundant memory cell within said memory cell array based on a redundant address signal.
Claim 19
Dependent Claim
51 words
The semiconductor memory as claimed in claim 14 wherein said redundant address switching circuit comprises a redundant address discriminating circuit for supplying to said first decoder means a signal for activating the redundant memory cell based on the redundant address signal and the output signals of each of said shift registers.
Claim 20
Dependent Claim
83 words
The semiconductor memory as claimed in claim 8 which further comprises redundant address generating means for generating a redundant address signal and a redundancy discriminating circuit for supplying to said first decoder means a redundancy switch signal for activating a redundant memory cell within said memory cell array when the address signal coincides with the redundant address signal, said redundant address generating means including redundant fuses which are selectively melted and cut depending on the redundant address signal which is to be generated.
Claim 21
Dependent Claim
28 words
The semiconductor memory as claimed in claim 16 wherein the redundant fuses of said redundant address generating means are grouped for each output signal of said register group.
Claim 22
Dependent Claim
31 words
The semiconductor memory as claimed in claim 17 wherein a number of groups of the redundant fuses is m+1 and a number of the redundant fuses within each group is n.
Claim 23
Dependent Claim
69 words
The semiconductor memory as claimed in claim 18 wherein said register group outputs an (m+1)-digit n-ary signal as said address signal, each of said shift registers outputting a corresponding one of m+1 digits of the n-ary signal, where the m+1 digits are n O , n 1 , . . ., n m , said redundant address generating means outputting an (m+1)-digit n-ary signal as said redundant address signal.
Claim 24
Dependent Claim
12 words
The semiconductor memory as claimed in claim 19 wherein m=2 and n=8.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-26 | 1995-11-25 | 1996-05-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-26 | 1999-11-25 | 2000-05-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-26 | 2003-11-25 | 2004-05-26 | $7700.00 | Window Closed / Lapsed |