Heterojunction method and structure

Claim 1

A method of fabricating heterojunction structures comprising the steps of: providing a semiconductor substrate; forming a plurality of semiconductor layers on said substrate, said plurality of semiconductor layers including a channel layer and at least one additional layer disposed on said channel layer; forming ohmic and gate contacts on said plurality of semiconductor layers; removing portions of said at least one additional layer of said plurality of semiconductor layers that are disposed between said ohmic and gate contacts wherein no portions of said channel layer are removed; forming gate metal on said gate contacts; forming source and drain regions in said plurality of semiconductor layers, the formation of said source and drain regions being self-aligned to said gate metal; and forming ohmic metal on said ohmic contacts.

Claim 2

A method of fabricating heterojunction structures comprising the steps of: providing a semiconductor substrate; forming a plurality of semiconductor layers on said substrate, said plurality of semiconductor layers including a channel layer and at least one additional layer disposed on said channel layer; forming ohmic and gate contacts on said plurality of semiconductor layers; removing portions of said at least one additional layer of said plurality of semiconductor layers that are disposed between said ohmic and gate contacts wherein no portions of said channel layer are removed; forming gate metal on said gate contacts; forming source and drain regions in said plurality of semiconductor layers, the formation of said source and drain regions being self-aligned to said gate metal; and forming ohmic metal on said ohmic contacts.

Claim 8

A method of fabricating a complementary HFET structure comprising the steps of: providing a gallium arsenide substrate; forming a plurality of compound semiconductor layers on said substrate; forming a tungsten nitride or tungsten based refractory metal contact layer on said plurality of compound semiconductor layers; forming ohmic and gate contacts from said contact layer; forming an N type channel region in said plurality of compound semiconductor layers of a first transistor structure; forming an N type well region in said plurality of compound semiconductor layers of a second transistor structure; forming a P type gate region in said plurality of compound semiconductor layers of said first transistor structure; etching the portions disposed between said ohmic and gate contacts of at least one of said plurality of compound semiconductor layers; selectively depositing tungsten gate metal on said gate contacts; forming N type source and drain regions in said first transistor structure and P type source and drain regions in said second transistor structure, the formation of said source and drain regions beings self-aligned to said gate metal; isolating said first and second transistor structures; and forming ohmic metal on said ohmic contacts.

Claim 9

A method of fabricating a complementary HFET structure comprising the steps of: providing a gallium arsenide substrate; forming a plurality of compound semiconductor layers on said substrate; forming a tungsten nitride or tungsten based refractory metal contact layer on said plurality of compound semiconductor layers; forming ohmic and gate contacts from said contact layer; forming an N type channel region in said plurality of compound semiconductor layers of a first transistor structure; forming an N type well region in said plurality of compound semiconductor layers of a second transistor structure; forming a P type gate region in said plurality of compound semiconductor layers of said first transistor structure; etching the portions disposed between said ohmic and gate contacts of at least one of said plurality of compound semiconductor layers; selectively depositing tungsten gate metal on said gate contacts; forming N type source and drain regions in said first transistor structure and P type source and drain regions in said second transistor structure, the formation of said source and drain regions beings self-aligned to said gate metal; isolating said first and second transistor structures; and forming ohmic metal on said ohmic contacts.