Semiconductor device

Claim 2

A semiconductor device having a heterojunction and utilizing a two-dimensional electron gas formed at said heterojunction, comprising: a substrate; a first semiconductor layer of undoped indium gallium arsenide formed on said substrate; a second semiconductor layer of n-type indium aluminum arsenide having top and bottom surfaces and formed with said bottom surface on said first semiconductor layer so as to define said heterojunction between said first semiconductor layer and said second semiconductor layer adjacent said bottom surface thereof; a third semiconductor layer of n-type gallium arsenide antimonide formed as a cap layer on the top surface of the second semiconductor layer and having a window defined therein so as to expose said top surface in a predetermined region thereof; a gate electrode provided in self-alignment with said window and in contact with said exposed top surface region of the second semiconductor layer; and ohmic electrodes formed on the cap layer in ohmic contact therewith.

Claim 3

A semiconductor device as claimed in claim 1 in which said substrate comprises indium phosphide and said first through third semiconductor layers have respective compositions which afford lattice matching with each other and with the substrate.

Claim 4

A semiconductor device as claimed in claim 1 in which said cap layer has a composition of GaAs x Sb 1-x in which x has a value of about 0.51.

Claim 5

A semiconductor device as claimed in claim 1 in which said ohmic electrodes comprise a first ohmic electrode formed at a first side of the gate electrode and a second ohmic electrode formed at a second, opposite side of the gate electrode.

Claim 6

A semiconductor device as claim in claim 4 further comprising an insulator layer formed on the third, semiconductor cap layer so as to isolate each of the first ohmic electrode and the second ohmic electrode from the gate electrode.

Claim 7

A semiconductor device comprising an enhancement-mode field effect transistor and a depletion-mode field effect transistor each having source, gate, and drain regions, said semiconductor device having a heterojunction and utilizing a two-dimensional electron gas formed at said heterojunction, comprising: a substrate; a first semiconductor layer of undoped indium gallium arsenide formed on said substrate; a second semiconductor layer of n-type indium aluminum arsenide formed on said first semiconductor layer so as to define said heterojunction between said first semiconductor layer and said second semiconductor layer, a first, predetermined region of the top surface of said second semiconductor layer being defined in correspondence to the position of a gate of said enhancement-mode field effect transistor; a third semiconductor layer of n-type gallium arsenide antimonide formed on the top surface of the second semiconductor layer, said third semiconductor layer having a first window defined therein, in correspondence to and for exposing said first, predetermined top surface region of said second semiconductor layer; a fourth semiconductor layer of n-type indium aluminum arsenide formed on said third semiconductor layer so as to cover at least a part of the third semiconductor layer by excluding at least said first window, a second, predetermined region of the top surface of said fourth semiconductor layer being defined in correspondence to the position of a gate of the depletion-mode type filed effect transistor; a fifth semiconductor layer of n-type gallium arsenide antimonide formed on said fourth semiconductor layer, said fifth semiconductor layer having a second window defined therein, in correspondence to and for exposing said second, predetermined top surface region of said fourth semiconductor layer; a first gate electrode, for said enhancement-mode filed effect transistor, formed in self-alignment with the first window and making a Schottky contact with said first top surface exposed region of said second semiconductor layer; a second gate electrode, for said depletion-mode field effect transistor formed in self-alignment with the second window and making a Schottky contact with said second top surface exposed region of said fourth semiconductor layer; and ohmic electrodes formed on said fifth semiconductor layer in ohmic contact therewith and in respective correspondence to source and drain electrodes of said enhancement-mode field effect transistor and of said depletion-mode field effect transistor.

Claim 8

A semiconductor device comprising an enhancement-mode field effect transistor and a depletion-mode field effect transistor each having source, gate, and drain regions, said semiconductor device having a heterojunction and utilizing a two-dimensional electron gas formed at said heterojunction, comprising: a substrate; a first semiconductor layer of undoped indium gallium arsenide formed on said substrate; a second semiconductor layer of n-type indium aluminum arsenide formed on said first semiconductor layer so as to define said heterojunction between said first semiconductor layer and said second semiconductor layer, a first, predetermined region of the top surface of said second semiconductor layer being defined in correspondence to the position of a gate of said enhancement-mode field effect transistor; a third semiconductor layer of n-type gallium arsenide antimonide formed on the top surface of the second semiconductor layer, said third semiconductor layer having a first window defined therein, in correspondence to and for exposing said first, predetermined top surface region of said second semiconductor layer; a fourth semiconductor layer of n-type indium aluminum arsenide formed on said third semiconductor layer so as to cover at least a part of the third semiconductor layer by excluding at least said first window, a second, predetermined region of the top surface of said fourth semiconductor layer being defined in correspondence to the position of a gate of the depletion-mode type filed effect transistor; a fifth semiconductor layer of n-type gallium arsenide antimonide formed on said fourth semiconductor layer, said fifth semiconductor layer having a second window defined therein, in correspondence to and for exposing said second, predetermined top surface region of said fourth semiconductor layer; a first gate electrode, for said enhancement-mode filed effect transistor, formed in self-alignment with the first window and making a Schottky contact with said first top surface exposed region of said second semiconductor layer; a second gate electrode, for said depletion-mode field effect transistor formed in self-alignment with the second window and making a Schottky contact with said second top surface exposed region of said fourth semiconductor layer; and ohmic electrodes formed on said fifth semiconductor layer in ohmic contact therewith and in respective correspondence to source and drain electrodes of said enhancement-mode field effect transistor and of said depletion-mode field effect transistor.

Claim 9

A semiconductor device as claimed in claim 6 in which said ohmic electrodes comprise a first ohmic electrode formed on said fifth semiconductor layer in ohmic contact therewith at a position located between respective, first sides of said first gate electrode and said second gate electrode, a second ohmic electrode formed on said fifth semiconductor layer at a second side, opposite to said first side, of said first gate electrode, and a third ohmic electrode formed on said fifth semiconductor layer at a second side, opposite to first side, of said second gate electrode.

Claim 10

A semiconductor device as claimed in claim 6 in which said semi-insulating substrate comprises indium phosphide and said first through fifth semiconductor layer have respective compositions which afford lattice matching with each other and with respect to said substrate.

Claim 11

A semiconductor device as claimed in claim 6, wherein each of said third and fifth semiconductor layers has a composition of GaAs x Sb 1-x , x having a value of about 0.51.