← Back to Patent Explorer
US4830980A Expired / Lapsed US ⏱️ 0.0 years remaining

Making complementary integrated p-MODFET and n-MODFET

Assignee: Raytheon Co
•
Filing: 1988-04-22
•
Granted: 1989-05-16
•
Expires: 2008-04-22
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract An integrated circuit device consisting of an n-channel selectively doped heterojunction transistor (SDHT) and a p-channel SDHT, in the form of complementary MODFETs fabricated on the same wafer, is disclosed. A method for easily fabricating the complementary p- and n-MODFETs on the same wafer is also disclosed whereby a portion of a partially formed n-channel SDHT is implanted with p-type ions of sufficient dosage to transform the portion into a p-channel SDHT. The device is completed by etching an isolation gap between the n-channel and p-channel region, preferably no more than ten microns wide, and adding ohmic source and drain contacts as well as Schottky gate contacts. Many such MODFET pairs may be fabricated on a single wafer.

Inventors

  • 👤 Kuan H. Hsieh

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 13:35
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/015; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/02; H10D84/05; H10D84/80; H10D84/86; H10W; H10W10/00; H10W10/01

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 194 words
An integrated circuit fabrication method for forming complementary field effect transistors on the same wafer substrate, comprising: epitaxially growing an intrinsic semiconductor buffer layer on a semiconductor substrate layer; epitaxially growing a semiconductor spacer layer on the buffer layer, said spacer layer being of different chemical composition and with a larger bandgap than said buffer layer; forming on said spacer layer an n-type doped semiconductor layer composed of the same material as said spacer layer; forming on said n-type doped layer a surface passivating n-type doped semiconductor cap layer composed of the same material as said buffer layer; implanting sufficient p-type ions into a selected portion of the n-type doped layer to transform said portion into a p-type layer; forming a pair of windows through the cap layer to expose portions of the n-type and p-type doped layers, respectively; forming a gap through the cap, semiconductor and the spacer layer and into the buffer layer to isolate the p-doped region from the n-doped region; and depositing respective source and drain contacts on the cap layer on opposite sides of each of said windows, and gate contacts on the underlying doped layers within said windows.
Claim 2
Dependent Claim 194 words
An integrated circuit fabrication method for forming complementary field effect transistors on the same wafer substrate, comprising: epitaxially growing an intrinsic semiconductor buffer layer on a semiconductor substrate layer; epitaxially growing a semiconductor spacer layer on the buffer layer, said spacer layer being of different chemical composition and with a larger bandgap than said buffer layer; forming on said spacer layer an n-type doped semiconductor layer composed of the same material as said spacer layer; forming on said n-type doped layer a surface passivating n-type doped semiconductor cap layer composed of the same material as said buffer layer; implanting sufficient p-type ions into a selected portion of the n-type doped layer to transform said portion into a p-type layer; forming a pair of windows through the cap layer to expose portions of the n-type and p-type doped layers, respectively; forming a gap through the cap, semiconductor and the spacer layer and into the buffer layer to isolate the p-doped region from the n-doped region; and depositing respective source and drain contacts on the cap layer on opposite sides of each of said windows, and gate contacts on the underlying doped layers within said windows.
Claim 3
Dependent Claim 11 words
The method of claim 1, wherein the p-type dopant comprises beryllium.
Claim 4
Dependent Claim 16 words
The method of claim 1, wherein said gap is no more than about ten microns wide.
Claim 5
Dependent Claim 30 words
The method of claim 3, further comprising the step of confining a two-dimensional electron gas (2DEG) at the non-implanted portions of the interface between the buffer and the spacer layer.
Claim 6
Dependent Claim 30 words
The method of claim 4, further comprising the step of confining a two-dimensional hole gas (2DHG) at the implanted portions of the interface between the buffer and the spacer layer.
Claim 7
Dependent Claim 31 words
The method of claim 5, wherein said 2DHG is formed by implanting sufficient p-type ions into a selected doped area of the 2DEG to transform said area into a 2DHG channel.

References Cited (Backward Citations)

US4641161A Cited
US4662058A Cited
US4603469A Cited
US4710478A Cited
US4652896A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-05-15 1992-11-14 1993-05-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-05-15 1996-11-14 1997-05-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-05-15 2000-11-14 2001-05-16 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag