Checkboard memory self-test

Claim 1

A method for a checkerboard self-test of memory circuits having a random pattern generator connected to address lines and data input lines thereof, the random pattern generator including means for stepping through each memory address, including a current memory address and a next memory address having a parity, during a random pattern generator cycle, the address lines including a least significant address line and a next least significant address line each having a binary state, the memory circuits having a multiple input signature register connected to output lines thereof, comprising the steps of: providing the random pattern generator with known seed data; continuously monitoring the parity of the current memory address and the next memory address to appear in the random pattern generator by using the binary state of the least significant and the next least significant address lines of the random pattern generator; writing checkerboard data into the memory circuits during a first random pattern generator cycle; outputting the checkerboard data from the memory circuits to the multiple input signature register during a second random pattern generator cycle; writing checkerboard data into the memory circuits during a third random pattern generator cycle, the data written during the third random pattern generator cycle being a complement of the data written during the first random pattern generator cycle; outputting the checkerboard data from the memory circuits to the multiple input signature register during a fourth random pattern generator cycle, thereby generating a data signature in the multiple input signature register; and comparing the data signature in the multiple input signature register with that which would be generated by the memory circuits if such are operating properly and provided with the same seed data.

Claim 2

A method for a checkerboard self-test of memory circuits having a random pattern generator connected to address lines and data input lines thereof, the random pattern generator including means for stepping through each memory address, including a current memory address and a next memory address having a parity, during a random pattern generator cycle, the address lines including a least significant address line and a next least significant address line each having a binary state, the memory circuits having a multiple input signature register connected to output lines thereof, comprising the steps of: providing the random pattern generator with known seed data; continuously monitoring the parity of the current memory address and the next memory address to appear in the random pattern generator by using the binary state of the least significant and the next least significant address lines of the random pattern generator; writing checkerboard data into the memory circuits during a first random pattern generator cycle; outputting the checkerboard data from the memory circuits to the multiple input signature register during a second random pattern generator cycle; writing checkerboard data into the memory circuits during a third random pattern generator cycle, the data written during the third random pattern generator cycle being a complement of the data written during the first random pattern generator cycle; outputting the checkerboard data from the memory circuits to the multiple input signature register during a fourth random pattern generator cycle, thereby generating a data signature in the multiple input signature register; and comparing the data signature in the multiple input signature register with that which would be generated by the memory circuits if such are operating properly and provided with the same seed data.

Claim 6

A method for a self-test of memory circuits having a random pattern generator connected to address lines and data input lines thereof, the random pattern generator including means for stepping through each memory address, including a current memory address and a next memory address having a parity, during a random pattern generator cycle, the address lines including a least significant address line and a next least significant address line each having a binary state, the memory circuits having a multiple input signature register connected to output lines thereof, comprising the steps of: providing the random pattern generator with known seed data; writing random data into the memory circuits during a first random pattern generator cycle; outputting data from the memory circuits to the multiple input signature register during a second random pattern generator cycle; writing random data into the memory circuits during a third random pattern generator cycle, the data written during the third random pattern generator cycle being a complement of the data written during the first random pattern generator cycle; outputting the random data from the memory circuits to the multiple input signature register during a fourth random pattern generator cycle; writing checkerboard data into the memory circuits during a fifth random pattern generator cycle; outputting the checkerboard data from the memory circuits to the multiple input signature register during a sixth random pattern generator cycle; writing checkerboard data into the memory circuits during a seventh random pattern generator cycle, the data written during the seventh random pattern generator cycle being a complement of the data written during the fifth random pattern generator cycle; outputting the checkerboard data from the memory circuits to the multiple input signature register during an eighth random pattern generator cycle, thereby generating a data signature in the multiple input signature register; continuously monitoring the parity of the current memory address and the next memory address to appear in the random pattern generator during the fifth and seventh random pattern generator cycles by using the binary state of the least significant and the next least significant address lines of the random pattern generator; and comparing the data signature in the multiple input signature register with that which would be generated by the memory circuits if such are operating properly and provided with the same seed data.

Claim 7

A method for a self-test of memory circuits having a random pattern generator connected to address lines and data input lines thereof, the random pattern generator including means for stepping through each memory address, including a current memory address and a next memory address having a parity, during a random pattern generator cycle, the address lines including a least significant address line and a next least significant address line each having a binary state, the memory circuits having a multiple input signature register connected to output lines thereof, comprising the steps of: providing the random pattern generator with known seed data; writing random data into the memory circuits during a first random pattern generator cycle; outputting data from the memory circuits to the multiple input signature register during a second random pattern generator cycle; writing random data into the memory circuits during a third random pattern generator cycle, the data written during the third random pattern generator cycle being a complement of the data written during the first random pattern generator cycle; outputting the random data from the memory circuits to the multiple input signature register during a fourth random pattern generator cycle; writing checkerboard data into the memory circuits during a fifth random pattern generator cycle; outputting the checkerboard data from the memory circuits to the multiple input signature register during a sixth random pattern generator cycle; writing checkerboard data into the memory circuits during a seventh random pattern generator cycle, the data written during the seventh random pattern generator cycle being a complement of the data written during the fifth random pattern generator cycle; outputting the checkerboard data from the memory circuits to the multiple input signature register during an eighth random pattern generator cycle, thereby generating a data signature in the multiple input signature register; continuously monitoring the parity of the current memory address and the next memory address to appear in the random pattern generator during the fifth and seventh random pattern generator cycles by using the binary state of the least significant and the next least significant address lines of the random pattern generator; and comparing the data signature in the multiple input signature register with that which would be generated by the memory circuits if such are operating properly and provided with the same seed data.

Claim 8

A system for checkerboard memory self-test comprising: a memory array having address lines, input lines, and output lines, the address lines including a least significant address line and a next least significant address line each having a binary state; a multiple input signature register connected to the output lines of the memory array; a random pattern generator connected to the address lines and input lines of the memory array, the random pattern generator capable of stepping through each memory address, including a current memory address and a next memory address having a parity; and means connected to the address lines and the input lines of the memory array for monitoring the parity of the current memory address and the next memory address to appear in the random pattern generator.

Claim 9

A system for checkerboard memory self-test comprising: a memory array having address lines, input lines, and output lines, the address lines including a least significant address line and a next least significant address line each having a binary state; a multiple input signature register connected to the output lines of the memory array; a random pattern generator connected to the address lines and input lines of the memory array, the random pattern generator capable of stepping through each memory address, including a current memory address and a next memory address having a parity; and means connected to the address lines and the input lines of the memory array for monitoring the parity of the current memory address and the next memory address to appear in the random pattern generator.

Claim 12

A system for functional and checkerboard memory self-test comprising: a memory array having address lines, input lines, and output lines; a multiple input signature register connected to the output lines of the memory array; a random pattern generator based upon a primitive polynomial and connected to the address lines and input lines of the memory array, the random pattern generator capable of stepping through each memory address, including a current memory address and a next memory address having a parity, the random pattern generator having at least one stage in addition to the number of address lines; and means connected to the address lines and the input lines of the memory array for monitoring the parity of the current memory address and the next memory address to appear in the random pattern generator.

Claim 13

A system for functional and checkerboard memory self-test comprising: a memory array having address lines, input lines, and output lines; a multiple input signature register connected to the output lines of the memory array; a random pattern generator based upon a primitive polynomial and connected to the address lines and input lines of the memory array, the random pattern generator capable of stepping through each memory address, including a current memory address and a next memory address having a parity, the random pattern generator having at least one stage in addition to the number of address lines; and means connected to the address lines and the input lines of the memory array for monitoring the parity of the current memory address and the next memory address to appear in the random pattern generator.