US3758759A
Expired / Lapsed
US
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Apparatus for determining partial memory chip categories
Assignee: Cogar Corp
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Filing: 1972-01-13
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Granted: 1973-09-11
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Expires: 1992-01-13
Abstract
Abstract There is disclosed an apparatus for determining partial memory chip categories. In the case of 128-cell chips having seven address bits, there are fourteen partial memory chip categories; permanently addressing any one of the seven address lines with a 1 or a 0 produces an effective 64-cell chip, any cell of which can be selected depending upon the address bits extended to the other six address lines. Each address bit of each bad cell on the chip causes a latch to be set as soon as it is determined that the cell is bad. Depending on its value, one of two respective partial chip categories is eliminated. After all cells have been tested the partial chip categories which have not been eliminated are those applicable to the chip, and they can be determined immediately from the settings of the latches.
Inventors
- 👤 C Boisvert
- 👤 A Mandia
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 15:07
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/04; G11C29/08; G11C29/12; G11C29/44
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
184 words
A chip testing system for automatically determining the partial memory categories, each having (N-1) effective address bits, applicable to a memory chip having 2N memory cells identifiable by N address bits, comprising means for representing N address bits of a cell to be tested, testing means for controlling the execution of a test operation on the cell identified by said represented address bits, 2N latch means each associated with one of the 2N partial memory categories with pairs of said latch means being associated with respective opposite bit values in a respective bit position in an N-bit address, means for setting all of said latches in a first state prior to the testing of a chip, means responsive to said Testing means detecting a bad cell for setting in a second state one of the two latches in each of the N pairs depending upon the value of the bit in the respective bit position of the address of the cell, and means for registering those latch means which are still in said first state at the end of the testing of said chip.
Claim 2
Dependent Claim
184 words
A chip testing system for automatically determining the partial memory categories, each having (N-1) effective address bits, applicable to a memory chip having 2N memory cells identifiable by N address bits, comprising means for representing N address bits of a cell to be tested, testing means for controlling the execution of a test operation on the cell identified by said represented address bits, 2N latch means each associated with one of the 2N partial memory categories with pairs of said latch means being associated with respective opposite bit values in a respective bit position in an N-bit address, means for setting all of said latches in a first state prior to the testing of a chip, means responsive to said Testing means detecting a bad cell for setting in a second state one of the two latches in each of the N pairs depending upon the value of the bit in the respective bit position of the address of the cell, and means for registering those latch means which are still in said first state at the end of the testing of said chip.
Claim 3
Dependent Claim
42 words
A chip testing system in accordance with claim 1 wherein said latch means are set in said second state in accordance with the address of a bad cell before the address bits in said representing means are changed to identify another cell.
Claim 4
Dependent Claim
174 words
A chip testing system for automatically determining the partial memory categories, each having (N-1) effective address bits, applicable to a memory chip having 2N memory cells identifiable by N address bits, comprising means for representing N address bits of a cell to be tested, testing means for controlling the exceution of a test operation on the cell identified by said represented address bits, 2N latch means each associated with one of the 2N partial memory categories with pairs of said latch means being associated with respective opposite bit values in a respective bit position in an N-bit address, means for setting all of said latches in a first state prior to the testing of a chip, means responsive to said testing means for setting in a second state each latch means whose respective bit value was represented in the respective bit position in the address of at least one bad cell, and means for registering those latch means which are still in said first state at the end of the testing of said chip.
Claim 5
Dependent Claim
174 words
A chip testing system for automatically determining the partial memory categories, each having (N-1) effective address bits, applicable to a memory chip having 2N memory cells identifiable by N address bits, comprising means for representing N address bits of a cell to be tested, testing means for controlling the exceution of a test operation on the cell identified by said represented address bits, 2N latch means each associated with one of the 2N partial memory categories with pairs of said latch means being associated with respective opposite bit values in a respective bit position in an N-bit address, means for setting all of said latches in a first state prior to the testing of a chip, means responsive to said testing means for setting in a second state each latch means whose respective bit value was represented in the respective bit position in the address of at least one bad cell, and means for registering those latch means which are still in said first state at the end of the testing of said chip.
Claim 6
Dependent Claim
42 words
A chip testing system in accordance with claim 3 wherein said latch means are set in said second state in accordance with the address of a bad cell before the address bits in said representing means are changed to identify another cell.
Claim 7
Dependent Claim
125 words
A chip testing system for automatically determining the partial memory categories applicable to a memory chip having a group of memory cells identifiable by a plurality of address bits comprising means for representing address bits of a cell to be tested, testing means for controlling the execution of a test operation on the cell identified by said represented address bits, registering means for representing partial memory categories for said chip to be eliminated, means responsive to said testing means for operating each of said registering means when its respective partial memory category must be eliminated by the represented address of at least one bad cell, and means for determining the partial memory categories applicable to a chip after it is tested from said registering means.
Claim 8
Dependent Claim
125 words
A chip testing system for automatically determining the partial memory categories applicable to a memory chip having a group of memory cells identifiable by a plurality of address bits comprising means for representing address bits of a cell to be tested, testing means for controlling the execution of a test operation on the cell identified by said represented address bits, registering means for representing partial memory categories for said chip to be eliminated, means responsive to said testing means for operating each of said registering means when its respective partial memory category must be eliminated by the represented address of at least one bad cell, and means for determining the partial memory categories applicable to a chip after it is tested from said registering means.
Claim 9
Dependent Claim
38 words
A chip testing system in accordance with claim 5 wherein said registering means are operated in accordance with the address of a bad cell before the address bits in said representing means are changed to identify another cell.
Claim 10
Dependent Claim
128 words
A chip testing system for automatically determining the partial operational categories applicable to a semiconductor chip having a group of logic circuits identifiable by a plurality of address bits comprising means for representing address bits of a logic circuit to be tested, testing means for controlling the execution of a test operation on the logic circuit identified by said represented address bits, registering means for representing partial memory categories for said chip to be eliminated, means responsive to said testing means for operating each of said registering means when its respective partial operational category must be eliminated by the represented address of at least one bad logic circuit, and means for determining the partial operational categories applicable to a chip after it is tested from said registering means.
Claim 11
Dependent Claim
128 words
A chip testing system for automatically determining the partial operational categories applicable to a semiconductor chip having a group of logic circuits identifiable by a plurality of address bits comprising means for representing address bits of a logic circuit to be tested, testing means for controlling the execution of a test operation on the logic circuit identified by said represented address bits, registering means for representing partial memory categories for said chip to be eliminated, means responsive to said testing means for operating each of said registering means when its respective partial operational category must be eliminated by the represented address of at least one bad logic circuit, and means for determining the partial operational categories applicable to a chip after it is tested from said registering means.
Claim 12
Dependent Claim
40 words
A chip testing system in accordance with claim 7 wherein said registering means are operated in accordance with the address of a bad logic circuit before the address bits in said representing means are changed to identify another logic circuit.
Claim 13
Independent Claim
108 words
A system for automatically dEtermining the partial memory categories applicable to a memory chip having a group of memory cells identifiable by a plurality of address bits comprising means for representing address bits of a cell, registering means for representing partial memory categories for said chip to be eliminated, means responsive to said testing means for operating each of said registering means when its respective partial memory category is indicated to be inapplicable to a memory chip by the represented address of at least one bad cell on the memory chip, and means for determining the partial memory categories applicable to the memory chip from said registering means.
Claim 14
Independent Claim
108 words
A system for automatically dEtermining the partial memory categories applicable to a memory chip having a group of memory cells identifiable by a plurality of address bits comprising means for representing address bits of a cell, registering means for representing partial memory categories for said chip to be eliminated, means responsive to said testing means for operating each of said registering means when its respective partial memory category is indicated to be inapplicable to a memory chip by the represented address of at least one bad cell on the memory chip, and means for determining the partial memory categories applicable to the memory chip from said registering means.
Claim 15
Dependent Claim
38 words
A chip testing system in accordance with claim 9 wherein said registering means are operated in accordance with the address of a bad cell before the address bits in said representing means are changed to identify another cell.
Claim 16
Independent Claim
110 words
A system for automatically determining the partial operational categories applicable to a logic chip having a group of logic circuits identifiable by a plurality of address bits comprising means for representing address bits of a logic circuit, registering means for representing partial memory categories for said chip to be eliminated, means responsive to said testing means for operating each of said registering means when its respective partial operational category is indicated to be inapplicable to a logic chip by the represented address of at least one bad logic circuit on the logic chip, and means for determining the partial operational categories applicable to the logic chip from said registering means.
Claim 17
Independent Claim
110 words
A system for automatically determining the partial operational categories applicable to a logic chip having a group of logic circuits identifiable by a plurality of address bits comprising means for representing address bits of a logic circuit, registering means for representing partial memory categories for said chip to be eliminated, means responsive to said testing means for operating each of said registering means when its respective partial operational category is indicated to be inapplicable to a logic chip by the represented address of at least one bad logic circuit on the logic chip, and means for determining the partial operational categories applicable to the logic chip from said registering means.
Claim 18
Dependent Claim
40 words
A chip testing system in accordance with claim 11 wherein said registering means are operated in accordance with the address of a bad logic circuit before the address bits in said representing means are changed to identify another logic circuit.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-09-10 | 1977-03-12 | 1977-09-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-09-10 | 1981-03-12 | 1981-09-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-09-10 | 1985-03-12 | 1985-09-11 | $7700.00 | Window Closed / Lapsed |