Patent US5097444A successfully refreshed from Google Patents.
US5097444A
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Tunnel EEPROM with overerase protection
Assignee: Rohm Usa Inc
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Filing: 1989-11-29
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Granted: 1992-03-17
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Expires: 2009-11-29
Abstract
Abstract The present invention provides protection against the effects of overerasure while essentially maintaining a single transistor per memory cell through the use of an additional transistor for each row of memory cells. The added transistor is a positive voltage threshold device which is coupled between the connected sources of the floating gate transistors and a read input line to limit the threshold voltage. For programming, a second transistor with a negative voltage threshold is coupled in the same manner, but is coupled to a program input line. The positive threshold transistor prevents an unselected transistor from turning on during a read operation.
Inventors
- 👤 Vincent L. Fong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 16:36
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; G11C16/06; G11C16/10; G11C16/14
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
112 words
An EEPROM comprising: a plurality of floating gate transistors forming a row of memory cells, each floating gate transistor having a first electrode coupled to a first node and a second electrode coupled to a corresponding column line; a positive threshold transistor having a gate coupled to a control gate of each of said floating gate transistors in said row, a first electrode coupled to said first node and a second electrode coupled to a read line; and a negative threshold transistor having a gate coupled to said control gates of said floating gate transistors, a first electrode coupled to said first node and a second electrode coupled to a program line.
Claim 2
Dependent Claim
112 words
An EEPROM comprising: a plurality of floating gate transistors forming a row of memory cells, each floating gate transistor having a first electrode coupled to a first node and a second electrode coupled to a corresponding column line; a positive threshold transistor having a gate coupled to a control gate of each of said floating gate transistors in said row, a first electrode coupled to said first node and a second electrode coupled to a read line; and a negative threshold transistor having a gate coupled to said control gates of said floating gate transistors, a first electrode coupled to said first node and a second electrode coupled to a program line.
Claim 3
Dependent Claim
15 words
The EEPROM of claim 1 wherein said positive threshold transistor is an N-channel enhancement transistor.
Claim 4
Dependent Claim
14 words
The EEPROM of claim 1 wherein said negative threshold transistor is a P-channel transistor.
Claim 5
Dependent Claim
19 words
The EEPROM of claim 1 wherein said first electrode of said floating gate transistors is a common N+ diffusion.
Claim 6
Dependent Claim
22 words
The EEPROM of claim 1 wherein said first electrode of said floating gate transistors is a source of said floating gate transistors.
Claim 7
Dependent Claim
59 words
The EEPROM of claim 1 further comprising means for programming one of said floating gate transistors by applying a first voltage to said read and program lines, an intermediate voltage to a drain of a selected floating gate transistor, and a first high voltage to said gates, said floating gate transistors having their sources coupled to said first node.
Claim 8
Dependent Claim
48 words
The EEPROM of claim 6 further comprising means for erasing one of said floating gate transistors by applying a high voltage to said program line with said control gates there of being grounded and said read line and a drain of each of said floating gate transistors floating.
Claim 9
Dependent Claim
16 words
The EEPROM of claim 1 wherein said floating gate transistors are programmed using hot electron injection.
Claim 10
Dependent Claim
15 words
The EEPROM of claim 1 wherein said floating gate transistors are programmed using electron tunneling.
Claim 11
Dependent Claim
129 words
An EEPROM comprising: a plurality of floating gate transistors forming a row of memory cells, each floating gate transistor being programmable using electron tunneling, each floating gate transistor having a source which is a common N+ diffusion forming a first node and having a drain connected to a corresponding column line; a positive threshold N-channel enhancement transistor having a gate coupled to a control gate of each of said floating gate transistors in said row, a first electrode coupled to said first node and a second electrode coupled to a read line; and a negative threshold transistor having a gate coupled to a control gate of each of said floating gate transistors, a first electrode coupled to said first node and a second electrode coupled to a program line.
Claim 12
Dependent Claim
129 words
An EEPROM comprising: a plurality of floating gate transistors forming a row of memory cells, each floating gate transistor being programmable using electron tunneling, each floating gate transistor having a source which is a common N+ diffusion forming a first node and having a drain connected to a corresponding column line; a positive threshold N-channel enhancement transistor having a gate coupled to a control gate of each of said floating gate transistors in said row, a first electrode coupled to said first node and a second electrode coupled to a read line; and a negative threshold transistor having a gate coupled to a control gate of each of said floating gate transistors, a first electrode coupled to said first node and a second electrode coupled to a program line.
Claim 13
Dependent Claim
14 words
The EEPROM of claim 10 wherein said negative threshold transistor is a P-channel transistor.
Claim 14
Dependent Claim
130 words
An EEPROM comprising: a plurality of floating gate transistors forming a row of memory cells, each floating gate transistors being programmable using hot electron injection, each floating gate transistor having a source which is a common N+) diffusion forming a first node and having a drain connected to a corresponding column line; a positive threshold N-channel enhancement transistor having a gate coupled to a control gate of each of said floating gate transistors in said row, a first electrode coupled to said first node and a second electrode coupled to a read line; and a negative threshold transistor having a gate coupled to a control gate of each of said floating gate transistors, a first electrode coupled to said first node and a second electrode coupled to a program line.
Claim 15
Dependent Claim
130 words
An EEPROM comprising: a plurality of floating gate transistors forming a row of memory cells, each floating gate transistors being programmable using hot electron injection, each floating gate transistor having a source which is a common N+) diffusion forming a first node and having a drain connected to a corresponding column line; a positive threshold N-channel enhancement transistor having a gate coupled to a control gate of each of said floating gate transistors in said row, a first electrode coupled to said first node and a second electrode coupled to a read line; and a negative threshold transistor having a gate coupled to a control gate of each of said floating gate transistors, a first electrode coupled to said first node and a second electrode coupled to a program line.
Claim 16
Dependent Claim
14 words
The EEPROM of claim 12 wherein said negative threshold transistor is a P-channel transistor.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1995-03-17 | 1995-09-16 | 1996-03-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-17 | 1999-09-16 | 2000-03-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-17 | 2003-09-16 | 2004-03-17 | $7700.00 | Window Closed / Lapsed |