Erase circuitry for a non-volatile semiconductor memory device

Claim 2

A non-volatile semiconductor memory device comprising: a memory cell array including a plurality of electrically erasable and programmable memory cell transistors, each memory cell transistor having a source region, a drain region, a floating gate, an erasing gate, and a control gate; selecting means coupled to the memory cell transistors of said memory cell array for selecting at lest one of said memory cell transistors; reading/writing means for reading data from and writing data to said memory cell transistors; erasing potential generating circuitry coupled to the erase gates of said memory cell transistors for generating an erasing potential which is applied to the erase gates of said memory cell transistors to erase data written therein in response to a first level of an erasing control signal; and source potential generating circuitry having an output node coupled to the source regions of said memory cell transistors for generating a source potential which is applied to the source regions of said memory cell transistors, said source potential generating circuitry including potential generating means for generating a first source potential at said output node when data is written to read from memory cell transistors and for, in response to the first level of the erasing control signal, generating a second source potential at said output node greater than the first source potential and less than the erasing potential when data is erased from memory cell transistors.

Claim 3

The non-volatile semiconductor memory device according to claim 1, wherein said potential generating means generates a ground potential at said output node of said source potential generating circuit as a first source potential which is applied to the source regions of said memory cell transistors when data is written to and read from said memory cell array.

Claim 4

The non-volatile semiconductor memory device according to claim 1, wherein said source potential generating circuitry comprises: a first inverter having an input node for receiving the erasing control signal and whose terminals are coupled between a first voltage source and a reference potential source; a second inverter having an input node coupled an output node of said first inverter and whose terminals are coupled between a second voltage source and said reference potential source, a voltage of said first voltage source being greater than a voltage of said second voltage source; and a switching circuit coupled between said input node of said second inverter and said second voltage source and controlled by an output signal at an output node of said second inverter to selectively switch the source potential at said output node of said source potential generating circuitry between the first and second source potentials.

Claim 5

The non-volatile semiconductor memory device according 3, further comprising: potential difference reducing means connected between said output node of said first inverter and said input node of said second inverter for reducing the potential difference between said output node of said first inverter and said input node of said second converter.

Claim 6

The non-volatile semiconductor memory device according 3, further comprising: potential difference reducing means connected between said output node of said first inverter and said input node of said second inverter for reducing the potential difference between said output node of said first inverter and said input node of said second converter.

Claim 7

The non-volatile semiconductor memory device according to claim 4, wherein said potential difference reducing means comprises: a first MOS transistor having a gate coupled to said first voltage source and a current path connected at a first end to said output node of said first inverter; and a second MOS transistor having a gate coupled to said second voltage source and a current path connected at a first end to a second end of the current path of said first MOS transistor and at a second end of the input node of said second inverter.

Claim 8

The non-volatile semiconductor memory device according to claim 3, wherein said second inverter comprises: a first MOS transistor of a first channel conductivity type having a gate coupled to said output node of said first inverter and a current path connected at a first end to said second voltage source; a second MOS transistor of a second channel conductivity type having a gate coupled to said output node of said first inverter and a current path connected at a first end to said reference potential source; and potential difference reducing means connected between a second end of the current path of said first MOS transistor and a second end of the current path of said second MOS transistor for reducing a potential difference therebetween, wherein said output node of said second inverter comprises a connection node between said first MOS transistor and said potential difference reducing means.

Claim 9

The non-volatile semiconductor memory according to claim 6 wherein said potential difference reducing means comprises: a third MOS transistor having a gate coupled to said second power source and a current path connected to a first end to the second end of the current path of said first MOS transistor; and a fourth MOS transistor having a gate coupled to said first power source and a current path connected at a first end to a second end of the current path of said third MOS transistor and at a second end to the second end of the current path of said second MOS transistor.

Claim 10

The non-volatile semiconductor memory device according to claim 7, wherein said first MOS transistor comprises a P-channel type MOS transistor and said second, third, and fourth MOS transistors comprise N-channel type MOS transistors.

Claim 11

The non-volatile semiconductor memory device according to claim 7, wherein said first MOS transistor comprises a P-channel type MOS transistor, said second MOS transistor comprises an N-channel MOS transistor, and said third and fourth MOS transistors comprise depletion type MOS transistors.

Claim 12

The non-volatile semiconductor memory device according to claim 3, wherein said switching circuit comprises: a MOS switching transistor having a gate coupled to said output node of said second inverter and a current path connected between said input node of said second inverter and said second voltage source.

Claim 13

The non-volatile semiconductor memory device according to claim 10, wherein said MOS switching transistor comprises a P-channel MOS transistor.

Claim 14

The non-volatile semiconductor memory device according to claim 3 further comprising: reducing means coupled to said output node of said second inverter for reducing a level of the output signal of said second inverter to provide the second source potential at said output node of said source potential generating circuitry in response to the first level of the erasing control signal.

Claim 15

The non-volatile semiconductor memory device according to claim 12 wherein said reducing means comprises: a first MOS transistor of a first channel conductivity type having a gate coupled to said output node of said second inverter and a current path connected at a first end to said second voltage source; a second MOS transistor of a second channel conductivity type having a gate coupled to said output node of said first inverter and a current path connected at a first end to said reference potential source; and potential difference reducing means connected between a second end of the current path of said first MOS transistor and a second end of the current path of said second MOS transistor for reducing a potential difference therebetween, wherein said output node of said source potential generating circuitry comprises a connection node between said first MOS transistor and said potential difference reducing means.

Claim 16

The non-volatile semiconductor memory device according to claim 13 wherein said potential difference reducing means comprises: a third MOS transistor having a gate coupled to said second voltage source and a current path connected at a first end to a second end of the current path of said first MOS transistor; and a fourth MOS transistor having a gate coupled to said first voltage source and a current path connected at a first end to a second end of the current path of said third MOS transistor and at a second end to a second end of the current path of said second MOS transistor.

Claim 17

The non-volatile semiconductor memory according to claim 14 wherein said first MOS transistor comprises a P-channel type MOS transistor and said second, third, and fourth MOS transistors comprise N-channel type MOS transistors.

Claim 18

The non-volatile semiconductor memory device according to claim 14 wherein said first MOS transistor comprises a P-channel type MOS transistor, said second MOS transistor comprises an N-channel MOS transistor, and said third and fourth MOS transistors comprise depletion type MOS transistors.

Claim 19

The non-volatile semiconductor memory device according to claim 3 further comprising: discharging means for discharging said output node of said source potential generating circuitry to set the first source potential when the erasing control signal switches from the first level to a second level; and delay means having an input node connected to said output node of said first inverter and coupled to said discharging means for delaying an application of a signal at said output node of said first inverter to said discharging means so as to delay discharging of said output node of said source potential generating circuitry for a predetermined time after said erasing control signal switches from the first level to the second level.

Claim 20

The non-volatile semiconductor memory device according to claim 17 wherein said delay means comprises: a plurality of inverters connected in cascade and each including an output node; a capacitor coupled between the output node of each inverter and said reference potential source; first switching means responsive to the first level of the erasing control signal for inhibiting a supply of power from said first voltage source to a final stage of said plurality of inverters; and second switching means responsive to the first level of the erasing control signal for supplying a reference potential to an output node of said final stage of said plurality of inverters.

Claim 21

The non-volatile semiconductor memory device according to claim 17 wherein said discharging means comprises: a first MOS transistor having a gate connected to said second voltage source and a current path connected at a first end to said output node of said source potential generating circuit; a second MOS transistor having a gate connected to said first voltage source and a current path connected at a first end to a second end of the current path of said first MOS transistor; and a third MOS transistor having a gate coupled to an output node of said delay means and a current path connected between the second end of the current path of said second MOS transistor and at a second end to said reference potential source.

Claim 22

The non-volatile semiconductor memory device according to claim 3 further comprising: a first MOS transistor of P-channel type having a gate coupled to said output node of said second inverter and a current path connected at a first end to said second voltage source; a second MOS transistor of depletion type having a gate coupled to said second voltage source and a current path connected at a first end to a second end of the current path of said first MOS transistor; a third MOS transistor of depletion type having a gate coupled to said first voltage source and a current path connected at a first end to a second end of the current path of said second MOS transistor; a fourth MOS transistor of N-channel type having a gate coupled to said output node of said second inverter and a current path connected at a first end to a second end of the current path of said third MOS transistor and at a second end to said reference potential source; a fifth MOS transistor of N-channel type having a gate coupled to said output node of said second inverter and a current path connected at a first end to said second voltage source; a sixth MOS transistor of depletion type having a gate coupled to said second voltage source and a current path connected at a first end to a second end of the current path of said fifth MOS transistor; a seventh MOS transistor of depletion type having a gate coupled to said first voltage source and a current path connected at a first end to a second end of the current path of said sixth MOS transistor; and an eighth MOS transistor of N-channel type having a gate coupled to a connection node between said first and second MOS transistors and a current path connected at a first end to a second end of the current path of said seventh MOS transistor and at a second end to said reference potential source, wherein said output node of said source potential generating circuit comprises a connection node between said fifth and sixth MOS transistors.

Claim 23

The non-volatile semiconductor memory device according to claim 3 wherein the first level of said source potential at said output node of said source potential generating circuitry is substantially the voltage level of said second power source and the second level of said source potential at said output node of said source potential generating circuitry is substantially ground potential.

Claim 24

The non-volatile semiconductor memory device according to claim 3, further comprising: reducing means for reducing a level of the voltage at said output node of said second inverter to provide a source potential at said output node of said source potential generating circuitry of a level lower than the potential at the output of said second inverter.

Claim 25

The non-volatile semiconductor memory device according to claim 22 wherein said reducing means comprises at least one MOS transistor whose gate is coupled to the output of said second inverter and one of whose source and drain regions is coupled to said second voltage source such that the source potential at said output node of said source potential generating circuitry is less than the potential at the output of said second inverter by an amount equal to a threshold voltage of said least one MOS transistor.

Claim 26

This non-volatile semiconductor memory device according to claim 1 wherein said source potential generating circuitry comprises: potential switching means coupled to receive the erasing control signal for switching the potential level of the erasing control signal between the voltage of said second voltage source and a group potential; charging means for charging said output node of said source potential generating circuitry in accordance with a potential at an output of said potential switching means; first discharging means for discharging said output node of said source potential generating circuitry in accordance with the erasing control signal; delay means for delaying the erasing control signal; and second discharging means for discharging said output node of said source potential generating circuitry in accordance with an output signal of said delay means.

Claim 27

The non-volatile semiconductor memory device according to claim 24 wherein said potential switching means comprises: an inverter having an input node for receiving the erasing control signal; a first MOS transistor of N-channel type having a gate coupled to receive the erasing control signal and a current path connected at a first end to a reference potential source; a second MOS transistor of N-channel type having a gate coupled to an output node of said inverter and a current path connected at a first end to said reference potential source; a third MOS transistor of depletion type having a gate coupled to said first voltage source and a current path connected at a first end to a second end of the current path of said first MOS transistor; a fourth MOS transistor of depletion type having a gate coupled to said first voltage source and a current path connected at a first end to a second end of the current path of said second MOS transistor; a fifth MOS transistor of P-channel type having a gate coupled to a second end of the current path of said fourth transistor and a current path connected between a second end of the current path of said third MOS transistor and said second voltage source; and a sixth MOS transistor of P-channel type having a gate coupled to a second end of the current path of said third transistor and a current path connected at a first end to a second end of the current path of said fourth MOS transistor and at a second end to said second power source, wherein an output node of said potential switching means comprises a connection node between said third and fifth MOS transistors.

Claim 28

The non-volatile semiconductor memory device according to claim 24, wherein said charging means comprises: a first MOS transistor of N-channel type having a gate and a first end of a current path thereof coupled to said second voltage source; and a second MOS transistor of P-channel type having a gate coupled to an output node of said potential switching means and a current path connected at a first end to a second end of the current path of said first MOS transistor and at a second end to said output node of said source potential generating means.

Claim 29

The non-volatile semiconductor memory device according to claim 24, wherein said first discharging means comprises: an inverter having an input node for receiving the erasing control signal; and an N-channel transistor having a gate connected to an output node of said inverter and a current path connected at a first end of said output node of said source potential generating circuitry and at a second end to said reference potential source.

Claim 30

The non-volatile semiconductor memory device according to claim 24, wherein said delay means comprises: a plurality of inverters connected in cascade and having respective output nodes; and capacitors connected between the output node of said inverters and said reference potential source.

Claim 31

The non-volatile semiconductor memory device according to claim 24, wherein said second discharging means comprises: a first MOS transistor of N-channel type having a gate coupled to receive the erasing control signal and a current path connected at a first end to said reference potential source; and a second MOS transistor of N-channel type having a gate coupled to an output node of said delay means and a current path connected at a first end to a second end of the current path of said first MOS transistor and at a second end to said reference potential source.

Claim 32

The non-volatile semiconductor memory device according to claim 24 further comprising: potential detecting means for detecting a potential of said output node of said source potential generating circuitry, wherein said delay means is controlled by an output signal of said potential detecting means.

Claim 33

The non-volatile semiconductor memory device according to claim 30, wherein said potential detecting means comprises: a first MOS transistor of P-channel type having a gate coupled to said output node of said source potential generating circuitry and a current path connected at a fist end to said first voltage source; a second MOS transistor of P-channel type having a gate coupled to receive the erasing control signal and a current path connected at a first end to a second end of the current path of said first MOS transistor; a third MOS transistor of N-channel type having a gate coupled to receive the erasing control signal and a current path connected at a first end to a second end of the current path of said second MOS transistor and at a second end to said reference potential source; an inverter having an input node connected to a connection node between said second and third MOS transistors and an output node connected to an input node of said delay means; and a fourth MOS transistor of N-channel type having a gate coupled to said output node of said source potential generating circuitry and a current path connected at a first end to said input node of said inverter and at a second end to said reference potential source.

Claim 34

The non-volatile semiconductor memory device according to claim 24, further comprising: third discharging means for discharging said output node of said source potential generating circuitry after said first discharging means starts to discharge said output node of said source potential generating circuitry and until said second discharging means starts to discharge said output node of said source potential generating circuitry.

Claim 35

The non-volatile semiconductor memory device according to claim 32, wherein said third discharging means comprises: an N-channel MOS transistor having a gate coupled to an intermediate stage of said delay means and a current path connected at a first end to said output node of said source potential generating circuitry and at a second end to said reference potential source.

Claim 36

The non-volatile semiconductor memory device according to claim 1, further comprising: erasing output detecting means for detecting an output of said erasing potential generating circuitry, wherein said source potential generating circuitry is responsive to said erasing output detecting means.

Claim 37

The non-volatile semiconductor memory device according to claim 34, wherein said erasing output detecting means comprises: a first MOS transistor of N-channel type having a gate coupled to said second voltage source and a current path connected at a first end to receive the erasing potential; a second MOS transistor of N-channel type having a gate coupled to a second end of the current path of said first MOS transistor and a current path connected at a first end to a reference potential source; a third MOS transistor of P-channel type having a gate coupled to said reference potential source and a current path connected at a first end to a second end of the current path of said second MOS transistor and at a second end to said first voltage source; and an inverter having an input node connected to a connection node between said second and third MOS transistors and an output node connected to a control input terminal of said source potential generating circuitry and whose terminals are coupled to said first voltage source and said reference potential source.

Claim 38

The non-volatile semiconductor memory device according to claim 34, wherein said erasing output detecting means comprises: a first MOS transistor of N-channel type having a gate coupled to said second voltage source and a current path connected at a first end to receive the erasing potential; a second MOS transistor of N-channel type having a gate coupled to a second end of the current path of said first transistor and a current path connected at a first end to a reference potential source; a third MOS transistor of N-channel type having a gate connected to said second voltage source and a current path connected at a first end to a second end of of the current path of said second MOS transistor; a fourth MOS transistor of P-channel type having a gate connected to said reference potential source and a current path connected at a first end to a second end of the current path of said third MOS transistor and at a second end to said second voltage source; and an inverter having an input node connected to a connection node between said third and fourth MOS transistors and an output node connected to a control input terminal of said source potential generating means and whose terminals are coupled to said first voltage source and said reference potential source.

Claim 39

A non-volatile semiconductor memory device according to claim 34, wherein said erasing output detecting means comprises: a first MOS transistor of N-channel type having a gate coupled to said second power source and a current path connected at a first end to receive the erasing potential; a second MOS transistor of N-channel type having a gate connected to the second end of the current path of said first MOS transistor and a current path connected at a first end to a reference potential source; a third MOS transistor of N-channel type having a gate connected to receive the erasing control signal and a current path connected at a first end to a second end of the current path of said second MOS transistor; a fourth MOS transistor of P-channel type having a gate connected to said reference potential source and a current path connected at a first end to a second end of the current path of said third MOS transistor and at a second end to said first voltage source; and an inverter having an input node connected to a connection node between said third and fourth MOS transistors and an output node connected to a control input terminal of said source potential generating circuitry and whose terminals are coupled between said first voltage source and said reference potential source.

Claim 40

A non-volatile semiconductor memory device according to claim 1, further comprising: erasing gate potential detecting means for detecting a potential of the erasing gate of each of said memory cell transistors, wherein said source potential generating circuitry is responsive to said erasing gate potential detecting means.

Claim 41

A non-volatile semiconductor memory device according to claim 38, wherein said source potential generating circuitry comprises: potential switching means connected to receive the erasing control signal and an output signal of said erasing gate potential detecting means for switching a level of the erasing control signal between the voltage level of said second voltage source and a ground potential when said erasing gate potential detecting means detects that the potential of the erasing gates has exceeded a predetermined potential level; charging means for charging said output node of said source potential generating circuitry in accordance with an output of said potential switching means; and first discharging means for discharging said output node of said source potential generating circuitry in accordance with said erasing control signal.

Claim 42

A non-volatile semiconductor memory device according to claim 39, wherein said source potential generating circuitry further comprises: delay means for delaying the erasing control signal; and second discharging means for discharging said output node of said source potential generating circuitry in accordance with an output signal of said delay means.

Claim 43

A non-volatile semiconductor memory device according to claim 40, wherein said source potential generating circuitry further comprises: third discharging means controlled by an intermediate state of said delay means for discharging said output stage node.

Claim 44

A non-volatile semiconductor memory device comprising: a memory cell array comprising a plurality of memory cell blocks each including electrically erasable and programmable memory cell transistors, each memory cell transistor having a source region, a drain region, a floating gate, an erasing gate, and a control gate; selecting means coupled to said memory cell transistors for selecting at least one of said memory cell transistors; reading/writing means for reading data from and writing data to said memory cell transistors; erasing potential generating circuits respectively coupled to said memory cell blocks; a block erasing decoder circuit for generating erasing control signals for controlling and erasing potential generating circuits, each of said erasing potential generating circuits generating an erasing potential which is applied to the erase gate of the memory cell transistors of the associated memory cell blocks to erase data written therein in response to a first level of a respective erasing control signal; and source potential generating circuits having output nodes and respectively coupled to said memory cell blocks for generating a source potential which is applied to the source regions of the memory cell transistors of the associated memory cell block, each of said source potential generating circuits including potential generating means for generating a first source potential at said output node when data is written to and read from the associated memory cell block and for, in response to the first level of the control signal, generating a second source potential at said output node greater than the first source potential and less than the erasing potential when data is erase from the associated memory cell blocks.

Claim 45

A non-volatile semiconductor memory device comprising: a memory cell array comprising a plurality of memory cell blocks each including electrically erasable and programmable memory cell transistors, each memory cell transistor having a source region, a drain region, a floating gate, an erasing gate, and a control gate; selecting means coupled to said memory cell transistors for selecting at least one of said memory cell transistors; reading/writing means for reading data from and writing data to said memory cell transistors; erasing potential generating circuits respectively coupled to said memory cell blocks; a block erasing decoder circuit for generating erasing control signals for controlling and erasing potential generating circuits, each of said erasing potential generating circuits generating an erasing potential which is applied to the erase gate of the memory cell transistors of the associated memory cell blocks to erase data written therein in response to a first level of a respective erasing control signal; and source potential generating circuits having output nodes and respectively coupled to said memory cell blocks for generating a source potential which is applied to the source regions of the memory cell transistors of the associated memory cell block, each of said source potential generating circuits including potential generating means for generating a first source potential at said output node when data is written to and read from the associated memory cell block and for, in response to the first level of the control signal, generating a second source potential at said output node greater than the first source potential and less than the erasing potential when data is erase from the associated memory cell blocks.