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US5089872A Expired / Lapsed US ⏱️ 0.0 years remaining

Selective germanium deposition on silicon and resulting structures

Assignee: North Carolina State University
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Filing: 1990-04-27
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Granted: 1992-02-18
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Expires: 2010-04-27
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Abstract

Abstract The invention is a method of selectively forming contacts on ultra shallow source and drain junctions. The method comprises forming a gate structure that defines a gate on a silicon substrate, portions of which are covered with a layer of silicon dioxide while the portions adjacent the gate form a silicon surface. The gate structure includes a surface material upon which germanium will not deposit at a temperature that is otherwise high enough to cause germanium to deposit from a germanium containing gas onto a silicon surface, but that is lower than the temperature at which germanium will deposit on the gate surface material. A source and drain are formed in the silicon substrate in the portions adjacent the gate by adding dopant atoms and in which the source and drain are separated by an active region of the silicon substrate defined by the gate structure. The substrate is then exposed to a germanium containing gas at a temperature high enough to cause the germanium to deposit from the germanium containing gas into the silicon surface but lower than the temperature at which the germanium will deposit on the gate structure surface material. The result is self-aligned germanium contacts to the source and the drain. The method can further comprise selectively depositing a metal on the germanium and annealing the deposit to form a germanide compound from the reaction between the deposited germanium and the deposited metal.

Inventors

  • 👤 Mehmet Ozturk
  • 👤 Jimmie Wortman
  • 👤 Douglas Grider

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 15:22
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/80; H10D62/83; H10D30/00; H10D30/60; H10D62/832; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0113; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259; H10D64/60; H10D64/62

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 212 words
A metal oxide semiconductor field effect transistor (MOSFET) characterized by high quality, low resistivity contacts and reduced size including shallow source and drain portions, and that can be manufactured in a low temperature, single chamber, self aligning process while avoiding unnecessary loss of silicon from a silicon containing substrate, said transistor comprising: a silicon substrate having a first conductivity type; an oxide layer upon a defined portion of said silicon substrate and that forms a gate oxide bordered on its sides by a silicon surface of said substrate; a gate contact upon said gate oxide that together with said gate oxide defines an active region of a gate channel in said substrate; respective source and drain portions in said substrate and having the opposite conductivity type from said substrate and forming respective p-n junctions with said substrate that are defined by said borders of said gate oxide with said silicon surface so that each said p-n junction is positioned directly beneath one of said borders of said gate oxide portion with said silicon surface and wherein said source and drain portions are respectively adjacent said bordered sides of said gate oxide; and ohmic contacts on said source and said drain selected from the group consisting of: germanium or a refractory metal germanide.
Claim 2
Dependent Claim 212 words
A metal oxide semiconductor field effect transistor (MOSFET) characterized by high quality, low resistivity contacts and reduced size including shallow source and drain portions, and that can be manufactured in a low temperature, single chamber, self aligning process while avoiding unnecessary loss of silicon from a silicon containing substrate, said transistor comprising: a silicon substrate having a first conductivity type; an oxide layer upon a defined portion of said silicon substrate and that forms a gate oxide bordered on its sides by a silicon surface of said substrate; a gate contact upon said gate oxide that together with said gate oxide defines an active region of a gate channel in said substrate; respective source and drain portions in said substrate and having the opposite conductivity type from said substrate and forming respective p-n junctions with said substrate that are defined by said borders of said gate oxide with said silicon surface so that each said p-n junction is positioned directly beneath one of said borders of said gate oxide portion with said silicon surface and wherein said source and drain portions are respectively adjacent said bordered sides of said gate oxide; and ohmic contacts on said source and said drain selected from the group consisting of: germanium or a refractory metal germanide.
Claim 3
Dependent Claim 13 words
A transistor according to claim 1 wherein said ohmic contacts comprise tungsten germanide.
Claim 4
Dependent Claim 67 words
A transistor according to claim 1 wherein said ohmic contacts comprise germanium and wherein said germanium contacts have a thickness sufficient to prevent a reaction between said germanium and a refractory metal from consuming silicon in said source and said drain when an amount of the refractory metal is used that will produce an amount of refractory metal germanide that will provide a substantially low resistivity contact.
Claim 5
Dependent Claim 105 words
A transistor according to claim 1 wherein said gate contact comprises: a layer of polycrystalline silicon upon said gate oxide, and wherein said layer of polycrystalline silicon is thick enough to support the deposition of polycrystalline germanium thereon while thin enough to be deposited rapidly enough to prevent damage to the gate oxide during the deposition process; and a layer of polycrystalline germanium on the layer of polycrystalline silicon, and wherein said layer of polycrystalline germanium is thick enough to prevent an ion implantation process form affecting said gate oxide when that ion implantation process is otherwise sufficient to dope said source and said drain.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1995-02-17 1995-08-19 1996-02-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1999-02-17 1999-08-19 2000-02-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2003-02-17 2003-08-19 2004-02-18 $7700.00 Window Closed / Lapsed

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