US4945393A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Floating gate memory circuit and apparatus
Assignee: Nokia Bell Labs
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Filing: 1989-12-07
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Granted: 1990-07-31
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Expires: 2009-12-07
Abstract
Abstract A floating gate memory device comprises a channel for conducting carriers from source to drain, a semiconductor heterostructure forming a potential well (floating gate) for confining carriers sufficiently proximate the channel so as to at least partially deplete it, and a graded bandgap injector region between the control gate and the floating gate for controlling the injection of carriers into and out of the potential well. Also described is a three element memory cell, including the memory device and two FETs, which operates from a constant, non-switched supply voltage and two-level control voltages. Arrays of memory devices may also be used to detect light in a variety of applications such as imaging.
Inventors
- 👤 Fabio Beltram
- 👤 Federico Capasso
- 👤 Roger J. Malik
- 👤 Nitin J. Shah
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 13:13
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0433; H; H10; H10D; H10D30/00; H10D30/80; H10D30/801; H10D30/803
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
204 words
A memory circuit comprising a plurality of write lines, read lines, power supply lines, and row select lines, a plurality of memory cells connected to said lines, each of said cells comprising a memory device which includes source, drain and control gate electrode means, a semiconductor channel for conducting carriers from said source to said drain means, and a semiconductor heterostructure disposed between said channel and control gate means, said heterostructure including a floating gate potential well for confining carriers in a region sufficiently close to said channel to at least partially deplete it and further including a graded bandgap injector region for controlling the flow of carriers between said control gate means and said potential well, said source means being connected to a source of reference potential, a first FET having its channel connected between said gate means of said memory device and one of said write lines, a second FET having its channel connected between said drain means of said memory device and one of said read lines and one of said power supply lines, the gates of said FETs being connected to one of said row select lines, and circuit means for maintaining the voltage on said supply line essentially constant.
Claim 2
Dependent Claim
204 words
A memory circuit comprising a plurality of write lines, read lines, power supply lines, and row select lines, a plurality of memory cells connected to said lines, each of said cells comprising a memory device which includes source, drain and control gate electrode means, a semiconductor channel for conducting carriers from said source to said drain means, and a semiconductor heterostructure disposed between said channel and control gate means, said heterostructure including a floating gate potential well for confining carriers in a region sufficiently close to said channel to at least partially deplete it and further including a graded bandgap injector region for controlling the flow of carriers between said control gate means and said potential well, said source means being connected to a source of reference potential, a first FET having its channel connected between said gate means of said memory device and one of said write lines, a second FET having its channel connected between said drain means of said memory device and one of said read lines and one of said power supply lines, the gates of said FETs being connected to one of said row select lines, and circuit means for maintaining the voltage on said supply line essentially constant.
Claim 3
Dependent Claim
125 words
The circuit of claim 1 further including a coding circuit comprising an array of inverters coupling a plurality of input lines, on which a byte of information to be stored is applied, to a corresponding plurality of output lines, each of which is coupled to a separate one of said write lines, means for receiving clock pulses, means for transferring a clock pulse unaltered to a write line whenever a bit from said byte on the corresponding input line is a logic "1", and means for inverting said clock pulse if the corresponding bit of said byte is a logic "0", said unaltered transfer and inverting occurring whenever said memory circuit utilizes negative clock pulses, and conversely whenever said memory circuit utilizes positive clock pulses.
Claim 4
Dependent Claim
133 words
Optical detection apparatus comprising an array of memory devices each comprising source, drain and control gate electrode means, a semiconductor channel for conducting carriers from said source to said drain means, and a semiconductor heterostructure disposed between said channel and control gate means, said heterostructure including a floating gate potential well for confining carriers in a region sufficiently close to said channel to at least partially deplete it and further including a graded bandgap injector region for controlling the flow of carriers between said control gate means and said potential well means for injecting carriers into the wells of said devices, means for making light incident on said array so as to remove carriers from at least one of said devices, thereby generating an electrical signal therefrom, and means for detecting said signal.
Claim 5
Dependent Claim
133 words
Optical detection apparatus comprising an array of memory devices each comprising source, drain and control gate electrode means, a semiconductor channel for conducting carriers from said source to said drain means, and a semiconductor heterostructure disposed between said channel and control gate means, said heterostructure including a floating gate potential well for confining carriers in a region sufficiently close to said channel to at least partially deplete it and further including a graded bandgap injector region for controlling the flow of carriers between said control gate means and said potential well means for injecting carriers into the wells of said devices, means for making light incident on said array so as to remove carriers from at least one of said devices, thereby generating an electrical signal therefrom, and means for detecting said signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-30 | 1994-01-29 | 1994-07-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-30 | 1998-01-29 | 1998-07-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-30 | 2002-01-29 | 2002-07-31 | $7700.00 | Window Closed / Lapsed |