Semiconductor memory device transistor and cell structure

Claim 1

DRAM semiconductor memory device, in which a semiconductive material wafer having a top surface is used as a substrate and the top surface is enhanced by deposition, etching and doping, the device comprising: a substrate; an oxide layer on the substrate defining active and isolation regions of the top surface, the isolation layers exhibiting an increase in thickness of the oxide layer over the active regions; the active regions forming a "dogbone" pattern, wherein each active region exhibits an elongate shape, with each end of the elongate shape being wider than a center leg of the elongate shape, the active regions being arrayed in alternating sequence such that the ends of alternating columns of the active regions nests with the center legs of alternate columns of the active regions; a first series of polysilicon overlays having center portions which overlap nested active regions at intersections of the center legs and the ends, and having extensions, each extending first parallel to the elongate shapes and then perpendicularly across an elongate shape at the center section, the first series of polysilicon overlays being etched in a pattern of transistor gates, thereby defining a series of transistors; a second series of polysilicon overlay forming a pattern of straight lines which alternately intersects the active regions across the center legs at the center of the center legs and passes between pairs of the ends; and each further polysilicon overlay having a contact pad on its center portion.