Semiconductor memory device

Claim 2

In a semiconductor device having a plurality of memory cells each coupled to a data line and having a word line, each memory cell being formed on a semiconductor substrate of a first conductivity type, said data line being formed of a semiconductor impurity region of a second conductivity type opposite to said first conductivity type formed in said semiconductor substrate, and each memory cell including a charge storage portion formed in said semiconductor substrate and a gate portion for forming a channel in said semiconductor substrate between said semiconductor impurity region and said charge storage portion, said word line being a metal conductive layer formed on said semiconductor substrate to overlie said charge storage portion and connected to said gate portion at a junction, said word line and said data line crossing each other with an insulating layer therebetween, the improvement wherein said word line has a first portion overlying said charge storage portion and a second portion overlying said data line, said first portion of said word line being of a width such that it completely overlies said charge storage portion, in width of said first portion being greater than the width of said second portion.

Claim 3

A semiconductor memory device having a plurality of memory cells each coupled to a data line and having a word line, each memory cell comprising: (a) a semiconductor substrate of a first conductivity type; (b) a semiconductor impurity region of a second conductivity type opposite to said first conductivity type formed in said semiconductor substrate; (c) a charge storage portion formed in said semiconductor substrate; (d) a gate portion coupled to said word line and formed on said semiconductor substrate between said semiconductor impurity region and said charge storage portion to form a channel therebetween; and (e) a data line of a metal conductive layer connected to said semiconductor impurity region at a junction and formed on said semiconductor substrate to completely overlay said charge storage portion.

Claim 4

A semiconductor memory device having a plurality of memory cells each coupled to a data line and having a word line, each memory cell comprising: (a) a semiconductor substrate of a first conductivity type; (b) a semiconductor impurity region of a second conductivity type opposite to said first conductivity type formed in said semiconductor substrate; (c) a charge storage portion formed in said semiconductor substrate; (d) a gate portion coupled to said word line and formed on said semiconductor substrate between said semiconductor impurity region and said charge storage portion to form a channel therebetween; and (e) a data line of a metal conductive layer connected to said semiconductor impurity region at a junction and formed on said semiconductor substrate to completely overlay said charge storage portion.

Claim 5

A semiconductor memory device according to claim 1, wherein a part of said charge storage portion is overlaid with another word line coupled to another memory cell.

Claim 6

In a semiconductor memory device having a plurality of memory cells each coupled to a word line and having first and second data lines, the data lines being metal conductive layers formed on a semiconductor substrate and each of the memory cells having first and second MOS transistors each having a drain, a source, and a gate, the sources of the first and second MOS transistors being connected to a reference potential point and the drains of the first and second MOS transistors being coupled respectively to the gates of the second and first MOS transistors at first and second output nodes, first and second resistors respectively connecting the first and second output nodes to a power supply, and third and fourth MOS transistors each having a drain, a source, and a gate, the gates of the third and fourth MOS transistors being connected to the word line, the source-drain path of the third MOS transistor being connected between the first output node and the first data line, and the source-drain path of the fourth MOS transistor being connected between the second output node and the second data line, each of the nodes comprising a semiconductor impurity region formed in the semiconductor substrate to store electric charge, the improvement wherein said impurity regions are formed to extend in parallel with each other, and said first and second data lines are formed so as to completely overlay said impurity regions forming said output nodes.

Claim 7

In a semiconductor memory device having a plurality of memory cells each coupled to a word line and having first and second data lines, the data lines being metal conductive layers formed on a semiconductor substrate and each of the memory cells having first and second MOS transistors each having a drain, a source, and a gate, the sources of the first and second MOS transistors being connected to a reference potential point and the drains of the first and second MOS transistors being coupled respectively to the gates of the second and first MOS transistors at first and second output nodes, first and second resistors respectively connecting the first and second output nodes to a power supply, and third and fourth MOS transistors each having a drain, a source, and a gate, the gates of the third and fourth MOS transistors being connected to the word line, the source-drain path of the third MOS transistor being connected between the first output node and the first data line, and the source-drain path of the fourth MOS transistor being connected between the second output node and the second data line, each of the nodes comprising a semiconductor impurity region formed in the semiconductor substrate to store electric charge, the improvement wherein said impurity regions are formed to extend in parallel with each other, and said first and second data lines are formed so as to completely overlay said impurity regions forming said output nodes.

Claim 8

A device as recited in claim 2 wherein said metal layer is formed of aluminum.

Claim 9

A device as recited in claim 2 wherein said charge storage portion is formed of an inversion layer.

Claim 10

A device as recited in claim 2 wherein said charge storage portion is formed of a semiconductor impurity region.

Claim 11

A device as recited in claim 2 wherein said charge storage portion is formed of a semiconductor impurity region and an inversion layer.