Semiconductor memory cell and method of manufacturing the same

Claim 1

A semiconductor memory comprising: a semiconductor substrate; a plurality of semiconductor memory cells formed in a matrix form on said semiconductor substrate; each semiconductor memory cells including a trench capacitor, a bit line, and a word line extending perpendicularly to said bit line, said trench capacitor including a charge storage insulating layer in a trench formed on said semiconductor substrate, a counter electrode formed on said insulating layer, a first active region formed at an open portion of said trench, and a second active region which is separate from said first active region formed on said semiconductor substrate, said word line being provided on said semiconductor substrate through an insulating layer which acts as a switching element in cooperation with said first and second active region, said bit line being coupled to said second active region, said switching element and said trench being arranged in a direction corresponding to the direction of said bit line, so that switching elements and trenches of neighboring cells are arranged reversely and in parallel t the bit line, and word lines of the semiconductor memory cells which are adjacent in the direction of said bit lines being arranged to be separate from each other at a portion in which switching elements are neighbors and to substantially vertically overlap each other at a portion in which said trenches are neighbors.