Semiconductor device and method of producing semiconductor device

Claim 2

A semiconductor device comprising: a semiconductor substrate of a first conductivity type having a first impurity concentration, said substrate having an exterior surface and said exterior surface having a gate region; a first belt-shaped impurity layer of said first conductivity type formed in said semiconductor substrate so as to be spaced apart from the exterior surface of said semiconductor substrate and which has a second impurity concentration which is higher than said first concentration at a first depth from the exterior surface of said semiconductor substrate, said first layer extending beneath the entirety of said gate region; a gate electrode having side walls formed on said semiconductor substrate at said gate region and a first insulating film interposed between said substrate and said gate electrode; two first impurity regions of a second conductivity type formed in said semiconductor substrate on both sides of said gate electrode so as to be spaced apart from each other and having a third impurity concentration at a second depth from the exterior surface of said semiconductor substrate, each region having a lower surface which is above said first impurity layer, said regions having a portion projecting downward of said gate electrode at a location adjacent to said first impurity layer; side wall insulating films each formed on a respective side wall of said gate electrode; and second impurity regions of said second conductivity type formed in said first regions laterally of said side wall insulating films and having a fourth impurity concentration higher than said third concentration, wherein said first impurity layer has a maximum impurity concentration at a depth of 0.2 to 0.7 μm from the exterior surface of said substrate.

Claim 3

A semiconductor device according to claim 1 wherein said second concentration of said first impurity layer has a maximum value in the range of 1×10 16 to 3×10 18 cm -3 .

Claim 4

A semiconductor device comprising: a semiconductor substrate of a first conductivity type having a first impurity concentration, said substrate having an exterior surface and said exterior surface having a gate region; a first belt-shaped impurity layer of said first conductivity type formed in said semiconductor substrate so as to be spaced apart from the exterior surface of said semiconductor substrate and which has a second impurity concentration which is higher than said first concentration at a first depth from the exterior surface of said semiconductor substrate, said first layer extending beneath the entirety of said gate region; a gate electrode having side walls formed on said semiconductor substrate at said gate region and a first insulating film interposed between said substrate and said gate electrode; two first impurity regions of a second conductivity type formed in said semiconductor substrate on both sides of said gate electrode so as to be spaced apart from each other and having a third impurity concentration at a second depth from the exterior surface of said semiconductor substrate, each region having a lower surface which is above said first impurity layer, said regions having a portion projecting downward of said gate electrode at a location adjacent to said first impurity layer; side wall insulating films each formed on a respective side wall of said gate electrode; and second impurity regions of said second conductivity type formed in said first regions laterally of said side wall insulating films and having a fourth impurity concentration higher than said third concentration. wherein said second concentration of said first impurity layer has a maximum value in the range of 1×10 16 to 3×10 18 cm -3 .

Claim 5

A semiconductor device comprising: a semiconductor substrate of a first conductivity type having a first impurity concentration, said substrate having an exterior surface and said exterior surface having a gate region; a first belt-shaped impurity layer of said first conductivity type formed in said semiconductor substrate so as to be spaced apart from the exterior surface of said semiconductor substrate and which has a second impurity concentration which is higher than said first concentration at a first depth from the exterior surface of said semiconductor substrate, said first layer extending beneath the entirety of said gate region; a gate electrode having side walls formed on said semiconductor substrate at said gate region and a first insulating film interposed between said substrate and said gate electrode; two first impurity regions of a second conductivity type formed in said semiconductor substrate on both sides of said gate electrode so as to be spaced apart from each other and having a third impurity concentration at a second depth from the exterior surface of said semiconductor substrate, each region having a lower surface which is above said first impurity layer, said regions having a portion projecting downward of said gate electrode at a location adjacent to said first impurity layer; side wall insulating films each formed on a respective side wall of said gate electrode; and second impurity regions of said second conductivity type formed in said first regions laterally of said side wall insulating films and having a fourth impurity concentration higher than said third concentration. wherein said second concentration of said first impurity layer has a maximum value in the range of 1×10 16 to 3×10 18 cm -3 .

Claim 6

A semiconductor device comprising: a semiconductor substrate of a first conductivity type having a first impurity concentration, said substrate having an exterior surface and said exterior surface having a gate region; a first belt-shaped impurity layer of said first conductivity type formed in said semiconductor substrate so as to be spaced apart from the exterior surface of said semiconductor substrate and which has a second impurity concentration which is higher than said first concentration at a first depth from the exterior surface of said semiconductor substrate, said first layer extending beneath the entirety of said gate region; a gate electrode having side walls formed on said semiconductor substrate at said gate region and a first insulating film interposed between said substrate and said gate electrode; two first impurity regions of a second conductivity type formed in said semiconductor substrate on both sides of said gate electrode so as to be spaced apart from each other and having a third impurity concentration at a second depth from the exterior surface of said semiconductor substrate, each region having a lower surface which is above said first impurity layer, said regions having a portion projecting downward of said gate electrode at a location adjacent to said first impurity layer; side wall insulating films each formed on a respective side wall of said gate electrode; and second impurity regions of said second conductivity type formed in said first regions laterally of said side wall insulating films and having a fourth impurity concentration higher than said third concentration. wherein said first impurity region has a maximum impurity concentration at a depth of 0.05 to 0.25 μm from the exterior surface of said substrate.

Claim 7

A semiconductor device comprising: a semiconductor substrate of a first conductivity type having a first impurity concentration, said substrate having an exterior surface and said exterior surface having a gate region; a first belt-shaped impurity layer of said first conductivity type formed in said semiconductor substrate so as to be spaced apart from the exterior surface of said semiconductor substrate and which has a second impurity concentration which is higher than said first concentration at a first depth from the exterior surface of said semiconductor substrate, said first layer extending beneath the entirety of said gate region; a gate electrode having side walls formed on said semiconductor substrate at said gate region and a first insulating film interposed between said substrate and said gate electrode; two first impurity regions of a second conductivity type formed in said semiconductor substrate on both sides of said gate electrode so as to be spaced apart from each other and having a third impurity concentration at a second depth from the exterior surface of said semiconductor substrate, each region having a lower surface which is above said first impurity layer, said regions having a portion projecting downward of said gate electrode at a location adjacent to said first impurity layer; side wall insulating films each formed on a respective side wall of said gate electrode; and second impurity regions of said second conductivity type formed in said first regions laterally of said side wall insulating films and having a fourth impurity concentration higher than said third concentration. wherein said first impurity region has a maximum impurity concentration at a depth of 0.05 to 0.25 μm from the exterior surface of said substrate.

Claim 8

A semiconductor device according to claim 4 wherein said third concentration of said first impurity region α has a maximum value in the range of ×10 16 to 6×10 18 cm -3 .

Claim 9

A semiconductor device comprising: a semiconductor substrate of a first conductivity type having a first impurity concentration, said substrate having an exterior surface and said exterior surface having a gate region; a first belt-shaped impurity layer of said first conductivity type formed in said semiconductor substrate so as to be spaced apart from the exterior surface of said semiconductor substrate and which has a second impurity concentration which is higher than said first concentration at a first depth from the exterior surface of said semiconductor substrate, said first layer extending beneath the entirety of said gate region; a gate electrode having side walls formed on said semiconductor substrate at said gate region and a first insulating film interposed between said substrate and said gate electrode; two first impurity regions of a second conductivity type formed in said semiconductor substrate on both sides of said gate electrode so as to be spaced apart from each other and having a third impurity concentration at a second depth from the exterior surface of said semiconductor substrate, each region having a lower surface which is above said first impurity layer, said regions having a portion projecting downward of said gate electrode at a location adjacent to said first impurity layer; side wall insulating films each formed on a respective side wall of said gate electrode; and second impurity regions of said second conductivity type formed in said first regions laterally of said side wall insulating films and having a fourth impurity concentration higher than said third concentration. wherein said third concentration of said first impurity region has a maximum value in the range of 1×10 16 to 6×10 18 cm -3 .

Claim 10

A semiconductor device comprising: a semiconductor substrate of a first conductivity type having a first impurity concentration, said substrate having an exterior surface and said exterior surface having a gate region; a first belt-shaped impurity layer of said first conductivity type formed in said semiconductor substrate so as to be spaced apart from the exterior surface of said semiconductor substrate and which has a second impurity concentration which is higher than said first concentration at a first depth from the exterior surface of said semiconductor substrate, said first layer extending beneath the entirety of said gate region; a gate electrode having side walls formed on said semiconductor substrate at said gate region and a first insulating film interposed between said substrate and said gate electrode; two first impurity regions of a second conductivity type formed in said semiconductor substrate on both sides of said gate electrode so as to be spaced apart from each other and having a third impurity concentration at a second depth from the exterior surface of said semiconductor substrate, each region having a lower surface which is above said first impurity layer, said regions having a portion projecting downward of said gate electrode at a location adjacent to said first impurity layer; side wall insulating films each formed on a respective side wall of said gate electrode; and second impurity regions of said second conductivity type formed in said first regions laterally of said side wall insulating films and having a fourth impurity concentration higher than said third concentration. wherein said third concentration of said first impurity region has a maximum value in the range of 1×10 16 to 6×10 18 cm -3 .

Claim 11

A semiconductor device comprising: a semiconductor substrate of a first conductivity type having a first impurity concentration, said substrate having an exterior surface and said exterior surface having a gate region; a first belt-shaped impurity layer of said first conductivity type formed in said semiconductor substrate so as to be spaced apart from the exterior surface of said semiconductor substrate and which has a second impurity concentration which is higher than said first concentration at a first depth from the exterior surface of said semiconductor substrate, said first layer extending beneath the entirety of said gate region; a gate electrode having side walls formed on said semiconductor substrate at said gate region and a first insulating film interposed between said substrate and said gate electrode; two first impurity regions of a second conductivity type formed in said semiconductor substrate on both sides of said gate electrode so as to be spaced apart from each other and having a third impurity concentration at a second depth from the exterior surface of said semiconductor substrate, each region having a lower surface which is above said first impurity layer, said regions having a portion projecting downward of said gate electrode at a location adjacent to said first impurity layer; side wall insulating films each formed on a respective side wall of said gate electrode; and second impurity regions of said second conductivity type formed in said first regions laterally of said side wall insulating films and having a fourth impurity concentration higher than said third concentration. wherein: said first impurity layer has a maximum impurity concentration at a depth of 0.2 to 0.7 μm from the exterior surface of said substrate; said second concentration of said first impurity layer has a maximum value in the range of 1×10 16 to 3×10 18 cm -3 ; said first impurity region has a maximum impurity concentration at a depth of 0.5 to 0.25 μm from the exterior surface of said substrate; and said third concentration of said first impurity region has a maximum value in the range of ×10 16 to 6×10 18 cm -3 .

Claim 12

A semiconductor device comprising: a semiconductor substrate of a first conductivity type having a first impurity concentration, said substrate having an exterior surface and said exterior surface having a gate region; a first belt-shaped impurity layer of said first conductivity type formed in said semiconductor substrate so as to be spaced apart from the exterior surface of said semiconductor substrate and which has a second impurity concentration which is higher than said first concentration at a first depth from the exterior surface of said semiconductor substrate, said first layer extending beneath the entirety of said gate region; a gate electrode having side walls formed on said semiconductor substrate at said gate region and a first insulating film interposed between said substrate and said gate electrode; two first impurity regions of a second conductivity type formed in said semiconductor substrate on both sides of said gate electrode so as to be spaced apart from each other and having a third impurity concentration at a second depth from the exterior surface of said semiconductor substrate, each region having a lower surface which is above said first impurity layer, said regions having a portion projecting downward of said gate electrode at a location adjacent to said first impurity layer; side wall insulating films each formed on a respective side wall of said gate electrode; and second impurity regions of said second conductivity type formed in said first regions laterally of said side wall insulating films and having a fourth impurity concentration higher than said third concentration. wherein: said first impurity layer has a maximum impurity concentration at a depth of 0.2 to 0.7 μm from the exterior surface of said substrate; said second concentration of said first impurity layer has a maximum value in the range of 1×10 16 to 3×10 18 cm -3 ; said first impurity region has a maximum impurity concentration at a depth of 0.5 to 0.25 μm from the exterior surface of said substrate; and said third concentration of said first impurity region has a maximum value in the range of ×10 16 to 6×10 18 cm -3 .