Semiconductor device and method of manufacturing the device

Claim 1

A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE, COMPRISING PROVIDING A LAYER MASKING AGAINST OXIDATION ON A PART OF THE SURFACE OF A FIRST REGION OF A FIRST CONDUCTIVITY TYP OF A SEMICONDUCTOR BODY, OXIDIZING THE BODY SURFACE PART NOT MASKED BY THE OXIDATION MASK UNTIL THERE IS FORMED A LAYER SHAPED OXIDE PATTERN WHICH IS AT LAST PARTLY INSET IN THE SEMICONDUCTOR BODY AND WHICH SUBSTANTIALLY ENTIRELY SURROUNDS A SURFACE PART OF THE FIRST REGION, INTRODUCINGFR FROM THE OUTSID INTO SAID SURFACE PART A DOPING MATERIAL DETERMINING THE SECCOND CONDUCTIVITY TYPE, THE INSET OXIDE PATTERN SERVING TO MASK T THE UNDERLYING BODY AGAINST SAID DOPING MATERIAL, INTRODUCING UNDERLYING BODY AGAINST SAID DOPING MATERIAL, INTRODUCING FROM THE OUTSIDE INTO SAID SECOND REGION VIA SPACED SURFACE PARTS THEREOF TO A DEPTH LESS THAN THE THICKNESS OF SAID SECOND REGION IN A DOPING MATERIAL DETERMINING FIRST CONDUCTIVITY TYPE TO FORM AT LAST SOURCE AND DRAIN ZONES OF A FIRST INSULATED GATE FIELD EFFECT TRANSISTOR, THE INSET OXIDE PATTERN AGAIN SERVING TO MASK THE UNDERLYING BODY PARTS AGAINST THE SAID DOPING MATERIAL AND DETERMINING A SUBSTANTIAL PART OF THE OUTER BOUNDARY OF THE SOURCE AND DRAIN ZONES, PROVIDING AT LEAST ONE GATE ELCTRODE LAYER WHICH IS SEPARATED FROM THE SECOND REGION BY AN ELECTRICALLY INSULATING LAYER AND WHICH EXTENDS ABOVE AT LEAST A PART OF THE SURFACE OF THE SECOND REGION BETWEEN THE SOURCE AND DRAIN ZONES, AND MAKING CONNECTIONS TO THE SOURCE AND DRAIN ZONES AND TO THE GATE.

Claim 2

A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE, COMPRISING PROVIDING A LAYER MASKING AGAINST OXIDATION ON A PART OF THE SURFACE OF A FIRST REGION OF A FIRST CONDUCTIVITY TYP OF A SEMICONDUCTOR BODY, OXIDIZING THE BODY SURFACE PART NOT MASKED BY THE OXIDATION MASK UNTIL THERE IS FORMED A LAYER SHAPED OXIDE PATTERN WHICH IS AT LAST PARTLY INSET IN THE SEMICONDUCTOR BODY AND WHICH SUBSTANTIALLY ENTIRELY SURROUNDS A SURFACE PART OF THE FIRST REGION, INTRODUCINGFR FROM THE OUTSID INTO SAID SURFACE PART A DOPING MATERIAL DETERMINING THE SECCOND CONDUCTIVITY TYPE, THE INSET OXIDE PATTERN SERVING TO MASK T THE UNDERLYING BODY AGAINST SAID DOPING MATERIAL, INTRODUCING UNDERLYING BODY AGAINST SAID DOPING MATERIAL, INTRODUCING FROM THE OUTSIDE INTO SAID SECOND REGION VIA SPACED SURFACE PARTS THEREOF TO A DEPTH LESS THAN THE THICKNESS OF SAID SECOND REGION IN A DOPING MATERIAL DETERMINING FIRST CONDUCTIVITY TYPE TO FORM AT LAST SOURCE AND DRAIN ZONES OF A FIRST INSULATED GATE FIELD EFFECT TRANSISTOR, THE INSET OXIDE PATTERN AGAIN SERVING TO MASK THE UNDERLYING BODY PARTS AGAINST THE SAID DOPING MATERIAL AND DETERMINING A SUBSTANTIAL PART OF THE OUTER BOUNDARY OF THE SOURCE AND DRAIN ZONES, PROVIDING AT LEAST ONE GATE ELCTRODE LAYER WHICH IS SEPARATED FROM THE SECOND REGION BY AN ELECTRICALLY INSULATING LAYER AND WHICH EXTENDS ABOVE AT LEAST A PART OF THE SURFACE OF THE SECOND REGION BETWEEN THE SOURCE AND DRAIN ZONES, AND MAKING CONNECTIONS TO THE SOURCE AND DRAIN ZONES AND TO THE GATE.

Claim 14

A method of manufacturing a CMOS semiconductor device, comprising the steps: a. providing an oxidation mask over spaced plural parts of the surface of a first region of a first type conductivity of a semiconductor body, b. thermally oxidizing the remaining exposed body surface areas until there is formed a layer shaped field oxide pattern at least partly inset in the semiconductor body and having portions entirely laterally surrounding at least first and second mesa portions of the first region lying underneath the oxidation mask, c. thereafter removing the oxidation mask oveR the first meas portion leaving the oxidation mask remaining over the second mesa portion, d. thereafter introducing from the outside into the first mesa portion second type conductivity dopants to form in the first mesa a second region of the second type conductivity, portions of the inset oxide serving to mask the underlying body against said second type dopants whereby the second region adjoins the inset oxide, e. introducing from the outside into the said second region via spaced surface parts thereof to a depth less than the thickness of said second region first type dopants to form at least source and drain zones of a first IGFET, portions of the inset oxide pattern serving at least in part to mask underlying body parts against the first type dopants whereby the source and drain zones adjoin portions of the inset oxide, f. removing the oxidation mask over the second mesa portion, g. introducing from the outside into the second mesa portion via spaced surface parts thereof second type dopants to form at least source and drain zones of a second IGFET complementary to the first, portions of the inset oxide pattern serving at least in part to mask underlying body parts against the second type dopants whereby the source and drain zones adjoin portions of the inset oxide, h. providing at least a first gate electrode which is separated from the second region by an electrically insulating layer and which extends above at least a part of the second region surface between the source and drain zones, and i. providing at least a second gate electrode which is separated from the second mesa by an electrically insulating layer and which extends above at least a part of the second mesa surface between the source and drain zones.

Claim 15

A method of manufacturing a CMOS semiconductor device, comprising the steps: a. providing an oxidation mask over spaced plural parts of the surface of a first region of a first type conductivity of a semiconductor body, b. thermally oxidizing the remaining exposed body surface areas until there is formed a layer shaped field oxide pattern at least partly inset in the semiconductor body and having portions entirely laterally surrounding at least first and second mesa portions of the first region lying underneath the oxidation mask, c. thereafter removing the oxidation mask oveR the first meas portion leaving the oxidation mask remaining over the second mesa portion, d. thereafter introducing from the outside into the first mesa portion second type conductivity dopants to form in the first mesa a second region of the second type conductivity, portions of the inset oxide serving to mask the underlying body against said second type dopants whereby the second region adjoins the inset oxide, e. introducing from the outside into the said second region via spaced surface parts thereof to a depth less than the thickness of said second region first type dopants to form at least source and drain zones of a first IGFET, portions of the inset oxide pattern serving at least in part to mask underlying body parts against the first type dopants whereby the source and drain zones adjoin portions of the inset oxide, f. removing the oxidation mask over the second mesa portion, g. introducing from the outside into the second mesa portion via spaced surface parts thereof second type dopants to form at least source and drain zones of a second IGFET complementary to the first, portions of the inset oxide pattern serving at least in part to mask underlying body parts against the second type dopants whereby the source and drain zones adjoin portions of the inset oxide, h. providing at least a first gate electrode which is separated from the second region by an electrically insulating layer and which extends above at least a part of the second region surface between the source and drain zones, and i. providing at least a second gate electrode which is separated from the second mesa by an electrically insulating layer and which extends above at least a part of the second mesa surface between the source and drain zones.