US5058007A — Next microinstruction generator in a microprogram…

Claim 1

Independent Claim 224 words

A microprogram control unit for generating microinstructions to control a data processing system comprising: memory means for storing a plurality of microinstructions; means coupled to address inputs of said memory means for providing to said memory means both a branch address from a current microinstruction being executed and a no-branch address for accessing said memory means sequentially during a current microinstruction cycle; means for selectively generating a first and a second enable signals in response to said current microinstruction; means coupled to said address providing means for incrementing the address coupled to said memory means in order to generate a next sequential address following a microinstruction being accessed by said address during said current microinstruction cycle; means coupled between an output of said incrementing means and an input of said address providing means for storing a next microinstruction address at the end of said current microinstruction cycle in response to said first and said second enable signals generated during said microinstruction cycle; means coupled to said memory means output for selecting a branch microinstruction or a no-branch microinstruction produced by said branch address and said no-branch address respectively, in response to said first and said second enable signals generated during said current microinstruction cycle; and means coupled to said selecting means for storing said selected microinstruction at the end of said current microinstruction cycle.

Claim 2

Dependent Claim 224 words

A microprogram control unit for generating microinstructions to control a data processing system comprising: memory means for storing a plurality of microinstructions; means coupled to address inputs of said memory means for providing to said memory means both a branch address from a current microinstruction being executed and a no-branch address for accessing said memory means sequentially during a current microinstruction cycle; means for selectively generating a first and a second enable signals in response to said current microinstruction; means coupled to said address providing means for incrementing the address coupled to said memory means in order to generate a next sequential address following a microinstruction being accessed by said address during said current microinstruction cycle; means coupled between an output of said incrementing means and an input of said address providing means for storing a next microinstruction address at the end of said current microinstruction cycle in response to said first and said second enable signals generated during said microinstruction cycle; means coupled to said memory means output for selecting a branch microinstruction or a no-branch microinstruction produced by said branch address and said no-branch address respectively, in response to said first and said second enable signals generated during said current microinstruction cycle; and means coupled to said selecting means for storing said selected microinstruction at the end of said current microinstruction cycle.

Claim 3

Dependent Claim 19 words

The microprogram control unit as recited in claim 1 wherein: said memory means comprises a read/write random access memory.

Claim 4

Dependent Claim 38 words

The microprogram control unit as recited in claim 2 wherein: said microprogram control unit further comprises a microprogram address buffer coupled to said memory means for providing addresses for loading said plurality of microinstructions into said memory means.

Claim 5

Dependent Claim 16 words

The microprogram control unit as recited in claim 1 wherein: said memory means comprises a read-only-memory.

Claim 6

Dependent Claim 24 words

The microprogram control unit as recited in claim 1 wherein: said branch address and said no-branch address providing means comprises a microprogram address register.

Claim 7

Dependent Claim 37 words

The microprogram control unit as recited in claim 1 wherein: a processing and branch control means coupled to said microprogram control unit provides control signals for selecting the next microinstruction based on said current microinstruction being executed.

Claim 8

Dependent Claim 34 words

The microprogram control unit as recited in claim 6 wherein: said control signals comprises a branch indicator generated by said processing and branch control means for selecting said branch microinstruction of said current microinstruction.

Claim 9

Dependent Claim 30 words

The microprogram control unit as recited in claim 6 wherein: said control signals comprises a hold indicator generated by said processing and branch control means for repeating said current microinstruction.

Claim 10

Dependent Claim 344 words

A microprogram control unit for controlling a data processor comprising: memory means for storing a plurality of microinstructions, each one of said microinstructions having a field which may be used as a branch address for addressing said memory means; address register means coupled to address inputs of said memory means for providing to said memory means in clocked sequence during a current microinstruction cycle both a branch address from a current microinstruction and a no-branch next address for accessing said memory means sequentially during said current microinstruction cycle; microinstruction selection and latching means coupled to the output of said memory means for providing during said current microinstruction cycle either a first output of said memory means in response to said branch address of a second output of said emory means in response to said no-branch next address in accordance with the state of a first and a second enable signals generated during said current microinstruction cycle; microinstruction register means, coupled to the output of said microinstruction selection and latching means, for storing said current microinstruction; incrementer means coupled to said address register means for computing a next address of a next microinstruction to follow the current microinstruction stored in said microinstruction register means; next address selection and latching means coupled to an output of said incrementer means for temporarily storing either the current output of said incrementer means of the previously latched output of said incrementer means in accordance with the state of said first and said second enable signals generated during said current microinstruction cycle; next address register means for storing the next sequential address after said current microinstruction, said next address register means having an input coupled to the output of said next address selection and latching means and an output coupled to said address register means input; and means for selectively generating a first and a second enable signals in response to said current microinstruction for gating said microinstruction selection and latching means and said address selection and latching means in accordance with control signals received during said current microinstruction cycle.

Claim 11

Dependent Claim 344 words

A microprogram control unit for controlling a data processor comprising: memory means for storing a plurality of microinstructions, each one of said microinstructions having a field which may be used as a branch address for addressing said memory means; address register means coupled to address inputs of said memory means for providing to said memory means in clocked sequence during a current microinstruction cycle both a branch address from a current microinstruction and a no-branch next address for accessing said memory means sequentially during said current microinstruction cycle; microinstruction selection and latching means coupled to the output of said memory means for providing during said current microinstruction cycle either a first output of said memory means in response to said branch address of a second output of said emory means in response to said no-branch next address in accordance with the state of a first and a second enable signals generated during said current microinstruction cycle; microinstruction register means, coupled to the output of said microinstruction selection and latching means, for storing said current microinstruction; incrementer means coupled to said address register means for computing a next address of a next microinstruction to follow the current microinstruction stored in said microinstruction register means; next address selection and latching means coupled to an output of said incrementer means for temporarily storing either the current output of said incrementer means of the previously latched output of said incrementer means in accordance with the state of said first and said second enable signals generated during said current microinstruction cycle; next address register means for storing the next sequential address after said current microinstruction, said next address register means having an input coupled to the output of said next address selection and latching means and an output coupled to said address register means input; and means for selectively generating a first and a second enable signals in response to said current microinstruction for gating said microinstruction selection and latching means and said address selection and latching means in accordance with control signals received during said current microinstruction cycle.

Claim 12

Dependent Claim 19 words

The microprogram control unit as recited in claim 9 wherein: said memory means comprises a read/write random access memory.

Claim 13

Dependent Claim 38 words

The microprogram control unit as recited in claim 9 wherein: said microprogram control unit further comprises a microprogram address buffer coupled to said memory means for providing addresses for loading said plurality of microinstruction into said memory means.

Claim 14

Dependent Claim 16 words

The microprogram control unit as recited in claim 9 wherein: said memory means comprises a read-only-memory.

Claim 15

Dependent Claim 50 words

The microprogram control unit as recited in claim 9 wherein: a processing and branch control means coupled to said enable signal generating means of said microprogram control unit provides control signals for generating said enable signal to participate in selecting said next microinstruction based on said current microinstruction being executed.

Claim 16

Dependent Claim 34 words

The microprogram control unit as recited in claim 13 wherein: said control signals comprises a branch indicator generated by said processing and branch control means for selecting a branch microinstruction to be executed next.

Claim 17

Dependent Claim 30 words

The microprogram control unit as recited in claim 13 wherein: said control signals comprises a hold indicator generated by said processing and branch control means for repeating said current microinstruction.

Claim 18

Dependent Claim 294 words

A microprogram control unit accessing microinstructions with both a sequential next address and a branch address within one microinstruction cycle comprising: memory means for storing a plurality of microinstructions, each one of said microinstructions having a field which may be used as said branch address for addressing said memory means; an address register coupled to said memory means for providing to said memory means in clocked sequence during a current microinstruction cycle both said branch address from a current microinstruction and said no-branch next address to fetch a next microinstruction within said one microinstruction cycle in accordance with the state of a first and a second enable signals; a microinstruction latch coupled to said memory means output for temporarily storing said fetched microinstruction; an address generator coupled to said address register for incrementing a microinstruction address to provide a next sequential address following a microinstruction being accessed during said microinstruction cycle; a next address latch coupled to the output of said next address generator for temporarily storing said generated next sequential address; a next address register coupled to said next address latch for storing said generated next sequential address, the output of said next address register being coupled to said address register input; a branch address latch coupled to said branch address field of said memory means output for temporarily storing said branch address of a current microinstruction, said address register input being coupled to said branch address latch output; and a latch enable generator having an output coupled to said next address latch, said branch address latch and said microinstruction latch, for selectively generating said first and said second enable signals during said current microinstruction cycle in accordance with the state of input control signals generated during the operation of said current microinstruction.

Claim 19

Dependent Claim 294 words

A microprogram control unit accessing microinstructions with both a sequential next address and a branch address within one microinstruction cycle comprising: memory means for storing a plurality of microinstructions, each one of said microinstructions having a field which may be used as said branch address for addressing said memory means; an address register coupled to said memory means for providing to said memory means in clocked sequence during a current microinstruction cycle both said branch address from a current microinstruction and said no-branch next address to fetch a next microinstruction within said one microinstruction cycle in accordance with the state of a first and a second enable signals; a microinstruction latch coupled to said memory means output for temporarily storing said fetched microinstruction; an address generator coupled to said address register for incrementing a microinstruction address to provide a next sequential address following a microinstruction being accessed during said microinstruction cycle; a next address latch coupled to the output of said next address generator for temporarily storing said generated next sequential address; a next address register coupled to said next address latch for storing said generated next sequential address, the output of said next address register being coupled to said address register input; a branch address latch coupled to said branch address field of said memory means output for temporarily storing said branch address of a current microinstruction, said address register input being coupled to said branch address latch output; and a latch enable generator having an output coupled to said next address latch, said branch address latch and said microinstruction latch, for selectively generating said first and said second enable signals during said current microinstruction cycle in accordance with the state of input control signals generated during the operation of said current microinstruction.

Claim 20

Dependent Claim 28 words

The microprogram control unit as recited in claim 16 herein: said microprogram control unit comprises a microinstruction register coupled to said microinstruction latch for storing said current microinstruction.

Claim 21

Dependent Claim 19 words

The microprogram control unit as recited in claim 16 wherein: said memory means comprises a read/write random access memory.

Claim 22

Dependent Claim 37 words

The microprogram control unit as recited in claim 16 wherein: said control unit further comprises a microprogram address buffer coupled to said memory means for providing addresses for loading said plurality of microinstruction into said memory means.

Claim 23

Dependent Claim 16 words

The microprogram control unit as recited in claim 16 wherein: said memory means comprises a read-only-memory.

Claim 24

Independent Claim 361 words

A method of generating a next microinstruction in a microprogram control unit of a data processing system comprising the steps of: storing a plurality of microinstructions in a memory means, each one of said microinstructions having a field which may be used as a branch address for addressing said memory means; providing to said memory means in clocked sequence during a current microinstruction cycle both a branch address from a current microinstruction and a no-branch address from a current microinstruction and a no-branch next address from an address register means coupled to address inputs of said memory means for accessing said memory means sequentially during said current microinstruction cycle in accordance with the state of a first and a second enable signals; providing in a microinstruction selection and latching means coupled to the output of said memory means during said current microinstruction cycle either a first output of said memory means in response to said branch address or a second output of said memory means in response to said non-branch next address in accordance with the state of said first and said second enable signals generated during said current microinstruction cycle; storing said current microinstruction in a microinstruction register means coupled to the output of said microinstruction selection and latching means; computing a next sequential address of a next microinstruction following the current microinstruction stored in said microinstruction register means with an incrementer means coupled to said address register means; storing in a next address selection and latching means coupled to an output of said incrementer means either the current output of said incrementer means or the previously latched output of said incrementer means in accordance with the state of said enable signal generated during said current microinstruction cycle; storing the next sequential address after said current microinstruction in a next address register means coupled to the output of said next address selection and latching means; and generating in a selective manner said first and said second enable signals in response to said current microinstruction for gating said microinstruction selection and latching means and said address selection and latching means in accordance with control signals received during said current microinstruction cycle.

Claim 25

Independent Claim 361 words

A method of generating a next microinstruction in a microprogram control unit of a data processing system comprising the steps of: storing a plurality of microinstructions in a memory means, each one of said microinstructions having a field which may be used as a branch address for addressing said memory means; providing to said memory means in clocked sequence during a current microinstruction cycle both a branch address from a current microinstruction and a no-branch address from a current microinstruction and a no-branch next address from an address register means coupled to address inputs of said memory means for accessing said memory means sequentially during said current microinstruction cycle in accordance with the state of a first and a second enable signals; providing in a microinstruction selection and latching means coupled to the output of said memory means during said current microinstruction cycle either a first output of said memory means in response to said branch address or a second output of said memory means in response to said non-branch next address in accordance with the state of said first and said second enable signals generated during said current microinstruction cycle; storing said current microinstruction in a microinstruction register means coupled to the output of said microinstruction selection and latching means; computing a next sequential address of a next microinstruction following the current microinstruction stored in said microinstruction register means with an incrementer means coupled to said address register means; storing in a next address selection and latching means coupled to an output of said incrementer means either the current output of said incrementer means or the previously latched output of said incrementer means in accordance with the state of said enable signal generated during said current microinstruction cycle; storing the next sequential address after said current microinstruction in a next address register means coupled to the output of said next address selection and latching means; and generating in a selective manner said first and said second enable signals in response to said current microinstruction for gating said microinstruction selection and latching means and said address selection and latching means in accordance with control signals received during said current microinstruction cycle.

Claim 26

Dependent Claim 227 words

In a microprogram control unit, a method of accessing microinstructions with both a sequential next address and a branch address within one microinstruction cycle comprising the steps of: storing a plurality of microinstructions in a memory means, each one of said microinstruction having a field which may be used as a branch address for addressing said memory means; providing to said memory means from an address register both a branch address from a current microinstruction and a no-branch next address for accessing said memory means in a clocked sequential manner within said one microinstruction cycle in accordance with the state of a first and a second enable signals; generating in a selective manner said first and said second enable signals in response to said current microinstruction; generating with incrementing means a next sequential address following said current microinstruction accessed from said memory means during said current microinstruction cycle; storing said next sequential address after said branch address or said no-branch address at the end of said current microinstruction cycle in response to said first and said second enable signals generated during said current microinstruction cycle; selecting a branch microinstruction or a no-branch microinstruction accessed from said memory means in response to said first and said second enable signals generated during said current microinstruction cycle; and storing said selected microinstruction at the end of said current microinstruction cycle.

Claim 27

Dependent Claim 227 words

In a microprogram control unit, a method of accessing microinstructions with both a sequential next address and a branch address within one microinstruction cycle comprising the steps of: storing a plurality of microinstructions in a memory means, each one of said microinstruction having a field which may be used as a branch address for addressing said memory means; providing to said memory means from an address register both a branch address from a current microinstruction and a no-branch next address for accessing said memory means in a clocked sequential manner within said one microinstruction cycle in accordance with the state of a first and a second enable signals; generating in a selective manner said first and said second enable signals in response to said current microinstruction; generating with incrementing means a next sequential address following said current microinstruction accessed from said memory means during said current microinstruction cycle; storing said next sequential address after said branch address or said no-branch address at the end of said current microinstruction cycle in response to said first and said second enable signals generated during said current microinstruction cycle; selecting a branch microinstruction or a no-branch microinstruction accessed from said memory means in response to said first and said second enable signals generated during said current microinstruction cycle; and storing said selected microinstruction at the end of said current microinstruction cycle.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1994-10-14	1995-04-15	1995-10-15	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1998-10-14	1999-04-15	1999-10-15	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2002-10-14	2003-04-15	2003-10-15	$7700.00	Window Closed / Lapsed

Next microinstruction generator in a microprogram control unit

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