US4124893A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microword address branching bit arrangement
Assignee: Bull HN Information Systems Inc
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Filing: 1976-10-18
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Granted: 1978-11-07
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Expires: 1996-10-18
Abstract
Abstract A digital computing system includes an addressable read only memory for storing microprogram control words. A plurality of the microprogram control words each include a predetermined bit used for branching. When the predetermined bit within a control word is not set, the next microprogram control word is read from the next microprogram memory address. When the predetermined bit is set, the next microprogram word is read from the microprogram memory address having a value which corresponds to the next address plus a weighted value of the predetermined bit.
Inventors
- 👤 Thomas F. Joyce
- 👤 Michel M. Raguin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 07:41
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/26; G06F9/262; G06F9/268
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
339 words
A data processing system comprising: at least one read only memory (ROM) for storing a plurality of microprograms, coupled to a ROM address register storing bits representative of a ROM address location, each microprogram comprising a plurality of microwords, said plurality of microwords comprising a first group of microwords and a second group of microwords, each microword of said first group having a plurality of coded bits designating a branch address for storing in said ROM address register, and said second group having at least two microwords each having a bit in a predetermined bit position for incrementing by a predetermined amount said ROM address register when said bit in said predetermined position is a binary ONE and a particular bit position in said ROM address register is a ZERO by said binary ONE, replacing said ZERO; a ROM local register (RSLR) coupled to said ROM for storing one of said plurality of microwords from said ROM address location during a first cycle of operation; said RSLR further coupled to said ROM address register for storing said branch address in said ROM address register during a second cycle of operation when one of said plurality of microwords of said first group is stored in said RSLR; decoding means coupled to said RSLR and responsive to a plurality of bits stored in said RSLR for detecting said one of at least two microwords of said second group when one of said plurality of microwords of said second group is stored in said RSLR; and Anding means coupled to said decoding means, said RSLR and said ROM address register, being responsive to said binary ONE bit stored in said predetermined position of said RSLR, and being further responsive to said decoding means detecting said one of at least two microwords of said second group and incrementing said ROM address register by said predetermined amount during said second cycle of operation when said particular bit position in said ROM address register contains said ZERO by replacing said ZERO by said binary ONE.
Claim 2
Dependent Claim
339 words
A data processing system comprising: at least one read only memory (ROM) for storing a plurality of microprograms, coupled to a ROM address register storing bits representative of a ROM address location, each microprogram comprising a plurality of microwords, said plurality of microwords comprising a first group of microwords and a second group of microwords, each microword of said first group having a plurality of coded bits designating a branch address for storing in said ROM address register, and said second group having at least two microwords each having a bit in a predetermined bit position for incrementing by a predetermined amount said ROM address register when said bit in said predetermined position is a binary ONE and a particular bit position in said ROM address register is a ZERO by said binary ONE, replacing said ZERO; a ROM local register (RSLR) coupled to said ROM for storing one of said plurality of microwords from said ROM address location during a first cycle of operation; said RSLR further coupled to said ROM address register for storing said branch address in said ROM address register during a second cycle of operation when one of said plurality of microwords of said first group is stored in said RSLR; decoding means coupled to said RSLR and responsive to a plurality of bits stored in said RSLR for detecting said one of at least two microwords of said second group when one of said plurality of microwords of said second group is stored in said RSLR; and Anding means coupled to said decoding means, said RSLR and said ROM address register, being responsive to said binary ONE bit stored in said predetermined position of said RSLR, and being further responsive to said decoding means detecting said one of at least two microwords of said second group and incrementing said ROM address register by said predetermined amount during said second cycle of operation when said particular bit position in said ROM address register contains said ZERO by replacing said ZERO by said binary ONE.
Claim 3
Dependent Claim
43 words
The data processing system as recited in claim 1 wherein said decoding means is comprised of a plurality of first AND gates and an OR gate, said first AND gates having their output terminals coupled to the input terminals of said OR gate.
Claim 4
Dependent Claim
52 words
The data processing system as recited in claim 2 wherein said ANDing means is comprised of second AND gate means having at least two input terminals with one of its input terminals coupled to the output terminal of said OR gate, and the second of its input terminals coupled to said RSLR.
Claim 5
Dependent Claim
58 words
The data processing system as recited in claim 3 wherein said RSLR is comprised of a plurality of flip-flops, each flip-flop having a "zero" output terminal and a "one" output terminal and wherein the second input terminal of said second AND gate means is coupled to the "one" terminal of a predetermined one of said plurality of flip-flops.
Claim 6
Dependent Claim
96 words
The data processing system as recited in claim 4 wherein said plurality of first AND gates is comprised of AND gate one and AND gate two and wherein all the input terminals of AND gate one are coupled to the "zero" terminal of the first three flip-flops of said RSLR, and all but one of the input terminals of AND gate two are coupled to the "zero" terminal of the first three flip-flops with the remaining input terminal of AND gate two being coupled to the "one" output terminal of the first flip-flop of said RSLR.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-11-06 | 1982-05-08 | 1982-11-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-11-06 | 1986-05-08 | 1986-11-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-11-06 | 1990-05-08 | 1990-11-07 | $7700.00 | Window Closed / Lapsed |