Instruction sequencer branch mechanism

Claim 2

Digital apparatus, comprising: memory means for containing a plurality of instructions; address means coupled to the memory means for providing address signals causing pairs of the instructions, comprising a primary instruction and a target instruction, to issue simultaneously from the memory means; register means for receiving and temporarily storing the pairs of instructions, the register means including a first and a second portion for respectively storing the primary and target instruction; decoding means coupled to the first portion of the register means for interpreting the primary instruction to provide control signals therefrom, the decoder means including a first circuit means for receiving at least one condition signal; and a second circuit means coupled to the register means and responsive to decoding of certain ones of the primary instructions by the decoder means and to presence of the condition signal for transferring the target instruction to the first portion of the register means.

Claim 3

The apparatus of claim 1, the second circuit means including means for transferring a segment of the primary instruction to the address menas to form address signals for accessing the memory means.

Claim 4

The apparatus in claim 1, including timer means operable to be initiated by the decoder means when certain of the primary instructions are interpreted for generating a time-out signal when the condition signal is absent for a predetermined period of time, the time-out signal for causing the address means to provide address signals to cause a next pair of instructions to issue from the memory means.

Claim 5

The apparatus of claim 3, the address means further comprising an incrementing means for incrementing a value held by the incrementing means and further wherein the address means functions also as said timer means.

Claim 6

In digital apparatus of the type operable to execute sequences of microinstructions supplied by a memory means in response to address signals from an address generating means, the apparatus having means functioning to generate control signals, and to respond to the presence of at least one condition signal, the improvement comprising the method of: sequentially accessing pairs of the microinstructions from the memory means simultaneously, each pair including of a primary microinstruction and a target microinstruction; decoding the primary microinstruction of each of the accesed pairs of microinstructions; responding to predetermined ones of the decoded primary microinstructions and to the presence of the condition signal to transfer a portion of the corresponding primary microinstruction to the address generating means as an address of a next sequential microinstruction pair and, at substantially the same time, to decode the target microinstructions of the pair of microinstructions.

Claim 7

In digital apparatus of the type operable to execute sequences of microinstructions supplied by a memory means in response to address signals from an address generating means, the apparatus having means functioning to generate control signals, and to respond to the presence of at least one condition signal, the improvement comprising the method of: sequentially accessing pairs of the microinstructions from the memory means simultaneously, each pair including of a primary microinstruction and a target microinstruction; decoding the primary microinstruction of each of the accesed pairs of microinstructions; responding to predetermined ones of the decoded primary microinstructions and to the presence of the condition signal to transfer a portion of the corresponding primary microinstruction to the address generating means as an address of a next sequential microinstruction pair and, at substantially the same time, to decode the target microinstructions of the pair of microinstructions.

Claim 8

The method of claim 5, including the step of holding the responding step, in absence of the condition signal, for (1) appearance of the condition signal or (2) appearance of a time-out signal indicative of expiration of a predetermined time period, whichever occurs first.

Claim 9

The method of claim 6, including the step of generating the time-out signal upon expiration of the predetermined time period.

Claim 10

The method of claim 5, including the step of, in the absence of the condition signal, accessing a next sequential pair of the microinstructions from the memory means.

Claim 11

Digital apparatus, comprising: memory means for containing a plurality of pairs of instructions, each pair of instructions including a primary instruction and a target instruction; address means coupled to the memory means for providing address signals causing pairs of the instructions to issue substantially simultaneously from the memory means; register means for receiving and temporaily storing the pairs of instruction, the register means including a first and a second portion for respectively storing the primary and target instructions; decoding means coupled to the first portion of the register means for interpreting the primary instruction to provide control signals therefrom, the decoder means including a first circuit means for receiving at least one condition signal; and second circuit means coulped to the register means and responsive to decoding of certain ones of the primary instructions by the decoder means and to the presence of the condition signals for communicating the target instruction to the decoding means for interpreting the target instruction, the second circuit means including means for transferring at least a segment of the primary instruction to the address means substantially simltaneous with the communication of the target instruction to the decoding means to form address signals for accessing the memory means.

Claim 12

Digital apparatus, comprising: memory means for containing a plurality of pairs of instructions, each pair of instructions including a primary instruction and a target instruction; address means coupled to the memory means for providing address signals causing pairs of the instructions to issue substantially simultaneously from the memory means; register means for receiving and temporaily storing the pairs of instruction, the register means including a first and a second portion for respectively storing the primary and target instructions; decoding means coupled to the first portion of the register means for interpreting the primary instruction to provide control signals therefrom, the decoder means including a first circuit means for receiving at least one condition signal; and second circuit means coulped to the register means and responsive to decoding of certain ones of the primary instructions by the decoder means and to the presence of the condition signals for communicating the target instruction to the decoding means for interpreting the target instruction, the second circuit means including means for transferring at least a segment of the primary instruction to the address means substantially simltaneous with the communication of the target instruction to the decoding means to form address signals for accessing the memory means.

Claim 13

Digital apparatus, comprising: memory means for storing a plurality of primary instructions and target instruction; address means coupled to the memory means for providing address signals causing a primary instruction and a target instruction to issue in parallel from the memory means; register means, including first and second portions for receiving and temporaily storing the primary and target instructions, respectively; control means coupled to the first portion of the register means for interpreting the primary instruction to provide control signals therefrom, the control means including a means for receiving at least one condition signal; circuit means coupled to the register means and responsive to the interpreting of certain ones of the primary instructions by the control means and to the presence of the condition signal for transferring the target instruction to the first portion of the register means; and, timer means operable to be initiated by the control means when the certain ones of the primary instructions are interpreted for generating a time-out signal when the condition signal is absent for a predetermined period of time, the time-out signals for causing the address means to provide address signals to cause pairs of instructions to issue from the memory means.

Claim 14

Digital apparatus, comprising: memory means for storing a plurality of primary instructions and target instruction; address means coupled to the memory means for providing address signals causing a primary instruction and a target instruction to issue in parallel from the memory means; register means, including first and second portions for receiving and temporaily storing the primary and target instructions, respectively; control means coupled to the first portion of the register means for interpreting the primary instruction to provide control signals therefrom, the control means including a means for receiving at least one condition signal; circuit means coupled to the register means and responsive to the interpreting of certain ones of the primary instructions by the control means and to the presence of the condition signal for transferring the target instruction to the first portion of the register means; and, timer means operable to be initiated by the control means when the certain ones of the primary instructions are interpreted for generating a time-out signal when the condition signal is absent for a predetermined period of time, the time-out signals for causing the address means to provide address signals to cause pairs of instructions to issue from the memory means.

Claim 15

The digital apparatus of claims 10, including means for presetting the timer means to a value indicative of the period of time.

Claim 16

The digital apparatus of claim 10, wherein the timer means includes presettable counter means operable to determine the period of time.

Claim 17

The digital apparatus of claim 12, including means for presetting the presettable counter means to predetermined values.

Claim 18

Digital apparatus comprising: memory means for storing a plurality of pairs of instructions, each of the pairs of instructions comprising a primary instruction and a target instruction; address means coupled to the memory means for providing address signals causing the pairs of instructions to sequentially issue from the memory means; first and second register means for receiving and temporarily storing the primary and target instructions, respectively; control means coulped to the first and second register means for interpreting the primary instruction to provide control signals therefrom, the control means including means for receiving at least one condition signal; and circuit means coupled to the first and second register means and responsive to the control signals and to the presence of the condition signal for transferring the target instruction to the first register means.

Claim 19

Digital apparatus comprising: memory means for storing a plurality of pairs of instructions, each of the pairs of instructions comprising a primary instruction and a target instruction; address means coupled to the memory means for providing address signals causing the pairs of instructions to sequentially issue from the memory means; first and second register means for receiving and temporarily storing the primary and target instructions, respectively; control means coulped to the first and second register means for interpreting the primary instruction to provide control signals therefrom, the control means including means for receiving at least one condition signal; and circuit means coupled to the first and second register means and responsive to the control signals and to the presence of the condition signal for transferring the target instruction to the first register means.

Claim 20

The digital appartus of claim 14, including timer means operable to be initiated by the control means when certain of the primary instructions of certain of the pairs of instructions are interpreted and the control signal is not present for generating a time-out signal for causing the address means to provide address signals to cause pairs of instructions to issue from the memory means when the condition signal has not appeared after a predetermined period of time.

Claim 21

The digital apparatus of claim 15, wherein the timer means includes a presettable counter.