Electronic calculator with display and keyboard scanning signal generator in data memory

Claim 2

An electronic calculator system comprising: a multiple digit display; a keyboard input means including a plurality of key switches arranged in groups; memory means including an array of memory cells; means for sequentially addressing the memory cells; arithmetic means for receiving data from the memory means and executing arithmetic functions on the data and returning it to the memory means; and means for generating timed signals for sequentially scanning the digits of the display and the groups of key switches, said means for generating timed signals comprising a first register having a plurality of bit positions, the first register being included in said memory means and being sequentially addressed with the cells thereof, means for entering a bit in a first bit position of the first register, sequential addressing of the memory cells causing said bit in the first register to be accessed once for each time a digit of the display is activated, feedback means receiving the bit accessed from the first register upon sequential addressing thereof and for shifting such bit by one bit position before returning such bit to the first register, and means responsive to the position of the bit in the first register for selecting digit positions in the memory means for reading out digits of data from the memory means to the display.

Claim 3

An electronic calculator system according to claim 1 wherein the means for generating timed signals includes a second register, the second register being a multiple stage shift register which is stepped in sequence, once for a complete addressing sequence of the memory cell and wherein stepping of the second register is initiated when the bit in the first register is in a selected position.

Claim 4

An electronic calculator system according to claim 2 further comprising output decode menas connected to said memory means for receiving digits of data from said memory means and reading out digits of data to the display as the memory cells are sequentially addressed.

Claim 5

An electronic calculator system according to claim 3 further comprising means connected to said first register and responsive to the position of the bit in the first register for selecting digits from the memory means for loading into the output decode means.

Claim 6

In an electronic calculator of the type implemented in a large-scale-integrated semiconductor circuit, a data memory for storing multiple digit data words, means for addressing the data memory one digit at a time, a multiple digit display, output means for reading out one digit at a time from the data memory to the display, and means for generating timed signals for actuating the digits of the display one at a time including a multiple digit register associated with the data memory, the multiple digit register being connected to the means for addressing the data memory and addressed simultaneously with the data memory for circulating a bit in synchronization with the timed signals, the position of the bit in the multiple digit register correlating with the timed signals and initiating generation of a sequence of the timed signals.

Claim 7

In an electronic calculator of the type implemented in a large-scale-integrated semiconductor circuit, a data memory for storing multiple digit data words, means for addressing the data memory one digit at a time, a multiple digit display, output means for reading out one digit at a time from the data memory to the display, and means for generating timed signals for actuating the digits of the display one at a time including a multiple digit register associated with the data memory, the multiple digit register being connected to the means for addressing the data memory and addressed simultaneously with the data memory for circulating a bit in synchronization with the timed signals, the position of the bit in the multiple digit register correlating with the timed signals and initiating generation of a sequence of the timed signals.

Claim 8

In a calculator according to claim 5, said means for generating timed signals further including means assocaited with said register for sequentially addressing all the digits of the data memory and the register in one entire cycle for each digit read out to the display.

Claim 9

In a calculator according to claim 6, control means in the output means, responsive to the position of the bit circulating in the register for selecting the digit to be read out from the data memory to the display.

Claim 10

In a calculator according to claim 7, a multiple stage scanning register included in the means for generating timed signals and responsive to the bit being in a selected digit position for beginning a scanning cycle of said timed signals.

Claim 11

In a calculator according to claim 5, loading means connected between the data memory and the output means, the loading means loading selected digits to be displayed into the output means in the order of most-significant-digit first, one digit being loaded after each time the bit circulating in the multiple digit register shifts in position.

Claim 12

In a calculator according to claim 9, the means for addressing the data memory functioning to sequentially address the data memory in the order of least-significant-digit first.

Claim 13

In an electronic calculator of the type implemented in a large-scale-integrated semiconductor circuit, an addressible data memory for temporarily storing multiple digit data words; a multiple digit display having two sets of input terminals, an actuating signal required at both sets to actuate the display; output means for reading out data in coded form of actuating signals from the data memory to the first set of input terminals of the display; actuating means for generating actuating signals in a predetermined order to the second set of the input terminals of the display one at a time, the actuating means including a multiple digit registr coupled to the data memory and addressed therewith, the content of the multiple digit register being employed for defining which input terminal of the display is to be actuated at a given time.

Claim 14

In an electronic calculator of the type implemented in a large-scale-integrated semiconductor circuit, an addressible data memory for temporarily storing multiple digit data words; a multiple digit display having two sets of input terminals, an actuating signal required at both sets to actuate the display; output means for reading out data in coded form of actuating signals from the data memory to the first set of input terminals of the display; actuating means for generating actuating signals in a predetermined order to the second set of the input terminals of the display one at a time, the actuating means including a multiple digit registr coupled to the data memory and addressed therewith, the content of the multiple digit register being employed for defining which input terminal of the display is to be actuated at a given time.

Claim 15

In a calculator according to claim 11, loading means, connected between the output means and the data memory, for loading a selected digit to be displayed from the data memory into the output means in the order of most-significant-digit first, one digit being loaded for each time an actuating signal actuates a digit of the display.

Claim 16

In a calculator according to claim 12, means, connected to said actuating means, for addressing the data memory and the multiple digit register one digit at a time in the order of least-significant-digit first.

Claim 17

In a calculator according to claim 13, means, connected to said actuating means, for blanking a plurality of said actuating signals during selected periods of operation of the calculator.

Claim 18

An electronic digital system comprising: a data memory in the form of an array of memory cells for storing a plurality of multiple digit data words; means for addressing the array of memory cells of the data memory by applying address signals to address lines in the array of memory cells; an array of key switches having a plurality of input terminals and a plurality of output terminals; display means having a plurality of inputs; scanning means for actuating in a preselected sequence certain ones of the plurality of inputs of the display means while at the same time actuating corresponding ones of the input terminals of the array of key switches in said preselected sequence; selection means including multi-bit register means included in the scanning means for defining the particular one of said plurality of inputs of the display means which is actuated at a given time, the multi-bit register means being connected to the means for addressing the array of memory cells of the data memory to receive the address signals applied to the address lines of the array of memory cells; and input means coupled to the output terminals of the array of said key switches for detecting closure of key switches.

Claim 19

An electronic digital system comprising: a data memory in the form of an array of memory cells for storing a plurality of multiple digit data words; means for addressing the array of memory cells of the data memory by applying address signals to address lines in the array of memory cells; an array of key switches having a plurality of input terminals and a plurality of output terminals; display means having a plurality of inputs; scanning means for actuating in a preselected sequence certain ones of the plurality of inputs of the display means while at the same time actuating corresponding ones of the input terminals of the array of key switches in said preselected sequence; selection means including multi-bit register means included in the scanning means for defining the particular one of said plurality of inputs of the display means which is actuated at a given time, the multi-bit register means being connected to the means for addressing the array of memory cells of the data memory to receive the address signals applied to the address lines of the array of memory cells; and input means coupled to the output terminals of the array of said key switches for detecting closure of key switches.

Claim 20

An electronic digital system according to claim 15 wherein the selection means includes a display scan register which contains a number of stages corresponding to the plurality of inputs of the display means which are actuated by the scanning means, and wherein the display scan register contains logic means for preventing actuation of selected ones of said plurality of inputs when in a nondisplaying mode to conserve system power.

Claim 21

An electronic digital system according to claim 15 wherein the data memory is addressed by said means for addressing in the order of least-signigicant-digit first, and wherein the scanning means actuates said certain ones of the plurality of inputs of the display means in the order of most-significant-digit first.

Claim 22

An electronic digital system according to claim 17 wherein the multi-bit register means includes means for shifting an accessed bit by one bit position in the direction of most-to-least-significant-digit each time the means for addressing the array of memory cells applies a complete sequence of address signals to the address lines of the array of memory cells.

Claim 23

An electronic digital system comprising: a data memory in the form of an array of memory cells for storing a plurlity of multiple digit data words; means for addressing the array of memory cells of the data memory by applying address signals to address lines in the array of memory cells; an array of key switches having a plurality of input terminals and a plurality of output terminals; display means having a plurality of input terminals; actuating means for actuating in a preselected sequence one set of the plurality of input terminals of the display means while at the same time actuating corresponding ones of the input terminals of the array of key switches in said preselected sequence; selection means included in the actuating means for selecting the particular one in said one set of input terminals of the display means which is to be actuated at a given time, the selection means including multi-stage memory means connected to the means for addressing the array of memory cells of the data memory to receive the address signals applied to the address lines of the array of memory cells; and input means coupled to the output terminals of the array of said key switches for detecting closure of key switches.

Claim 24

An electronic digital system comprising: a data memory in the form of an array of memory cells for storing a plurlity of multiple digit data words; means for addressing the array of memory cells of the data memory by applying address signals to address lines in the array of memory cells; an array of key switches having a plurality of input terminals and a plurality of output terminals; display means having a plurality of input terminals; actuating means for actuating in a preselected sequence one set of the plurality of input terminals of the display means while at the same time actuating corresponding ones of the input terminals of the array of key switches in said preselected sequence; selection means included in the actuating means for selecting the particular one in said one set of input terminals of the display means which is to be actuated at a given time, the selection means including multi-stage memory means connected to the means for addressing the array of memory cells of the data memory to receive the address signals applied to the address lines of the array of memory cells; and input means coupled to the output terminals of the array of said key switches for detecting closure of key switches.

Claim 25

An electronic digital system according to claim 19 wherein the multi-stage memory means contains a data bit corresponding to the particular one in said one set of input terminals of the display means which is actuated at a given time.

Claim 26

An electronic digital system according to claim 20 wherein means are provided for shifting said data bit by one bit position in the multistage memory means in a direction of from most-to-least-significant-digit each time the means for addressing the array of memory cells applies a complete sequence of address signals to the address lines in the array of memory cells.

Claim 27

An electronic calculator comprising: a data memory in the form of an array of memory cells for storing a plurality of multiple digit data words; means for addressing the array of memory cells of the data memory by applying address signals to address lines in the array of memory cells; an array of key switches having a plurality of input terminals and a plurality of output terminals; multiple digit display means having a plurality of input terminals; actuating means for actuating in a preselected sequence one set of the plurality of input terminals of the display means while at the same time actuating corresponding ones of the input terminals of the array of key switches in said preselected sequence; selection means included in the actuating means for selecting the particular one in said one set of input terminals of the display means which is to be actuated at a given time, the selection means including multi-stage memory means connected to the means for addressing the array of memory cells of the data memory to receive the address signals applied to the address lines of the array of memory cells; input means coupled to the output terminals of the array of said key switches for detecting closure of said key; and output decode and storage means, connected to the data memory and to another set of the input terminals of the display means, for converting said data words stored in said data memory into actuating signals for actuating selected ones of said another set of input terminals to provide a visual display of said data words.

Claim 28

An electronic calculator comprising: a data memory in the form of an array of memory cells for storing a plurality of multiple digit data words; means for addressing the array of memory cells of the data memory by applying address signals to address lines in the array of memory cells; an array of key switches having a plurality of input terminals and a plurality of output terminals; multiple digit display means having a plurality of input terminals; actuating means for actuating in a preselected sequence one set of the plurality of input terminals of the display means while at the same time actuating corresponding ones of the input terminals of the array of key switches in said preselected sequence; selection means included in the actuating means for selecting the particular one in said one set of input terminals of the display means which is to be actuated at a given time, the selection means including multi-stage memory means connected to the means for addressing the array of memory cells of the data memory to receive the address signals applied to the address lines of the array of memory cells; input means coupled to the output terminals of the array of said key switches for detecting closure of said key; and output decode and storage means, connected to the data memory and to another set of the input terminals of the display means, for converting said data words stored in said data memory into actuating signals for actuating selected ones of said another set of input terminals to provide a visual display of said data words.

Claim 29

An electronic calculator according to claim 22 wherein the multi-stage memory contains a data bit corresponding to the particular one in said one set of input terminals of the display means which is actuated at a given time.

Claim 30

An electronic calculator according to claim 23 wherein the actuating means actuates said one set of input terminals of the display means in the order of most-to-least-significant-digit.

Claim 31

An electronic calculator according to claim 22 wherein all of the circuitry of the data memory, the means for addressing the data memory, the selection means, and the output decode and storage means is contained within a single large-scale-integrated semiconductor device along with arithmetic means coupled to the data memory for permorming computational operations on the multiple digit data words. performing