US3639742A
Expired / Lapsed
US
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Number positioning display for electronic calculating machines
Assignee: Bell Punch Co Ltd
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Filing: 1969-02-28
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Granted: 1972-02-01
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Expires: 1989-02-28
Abstract
Abstract A calculating system employing a numerical display is described with a plurality of number display tubes each having a corresponding register for storing the number to be displayed. Numbers may be transferred from one register stage to another and the value of each of the digits is determined to present the highest significant digit at a predetermined stage by way of transfer in the stages.
Inventors
- 👤 James John Drage
- 👤 Norbert Kitz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 08:55
CPC Classifications
G; G09; G09G; G09G3/00; G09G3/04; G09G3/06; G09G3/10
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
221 words
A calculating machine comprising a number store register having a plurality of register stages for storing digit pulses representative of the digits of a number entered in the number store register; a multistage display device for displaying the digits of the number stored in the number store register, each stage in the display device being designated to display a particular digit of a number stored in the register stages; shifting means for transferring the digit pulses representative of the number from one register stage to another of the plurality of register stages; means for detecting the presence of a digit pulse of predetermined value at a particular register stage, display timer transfer means causing the digit pulse of the number entered in the particular register stage to be displayed at a predetermined stage in the display device designated for that digit of the number in the number store register; a circuit connecting the stages of the number store register to form an endless loop shift register circuit; said transfer means comprising a first set of AND gates, and a circuit connecting at least one input of said gates to the number store register and to a particular stage of the display device to display the highest significant digit of the number stored in the register at a predetermined display device stage.
Claim 2
Dependent Claim
221 words
A calculating machine comprising a number store register having a plurality of register stages for storing digit pulses representative of the digits of a number entered in the number store register; a multistage display device for displaying the digits of the number stored in the number store register, each stage in the display device being designated to display a particular digit of a number stored in the register stages; shifting means for transferring the digit pulses representative of the number from one register stage to another of the plurality of register stages; means for detecting the presence of a digit pulse of predetermined value at a particular register stage, display timer transfer means causing the digit pulse of the number entered in the particular register stage to be displayed at a predetermined stage in the display device designated for that digit of the number in the number store register; a circuit connecting the stages of the number store register to form an endless loop shift register circuit; said transfer means comprising a first set of AND gates, and a circuit connecting at least one input of said gates to the number store register and to a particular stage of the display device to display the highest significant digit of the number stored in the register at a predetermined display device stage.
Claim 3
Dependent Claim
155 words
A calculating machine according to claim 1, wherein the calculating machine further includes a master oscillator; and input decade counter with 11 outputs connected to the output of the master oscillator to divide the continuously generated oscillator pulses into a continuous sequence of trains of 10 pulses which appear on 10 outputs respectively with each train of pulses being separated from the next train of pulses by a shift pulse which appears on a shift pulse output; and a timer circuit in said display timer transfer means having a number of outputs equal to the number of stages in the number store register, the input of the timer circuit being connected to the output of the one input of said gates to the number store register and to a particular stage of the display device to display the highest significant digit of the number stored in the register at a predetermined display device stage. 0
Claim 4
Dependent Claim
211 words
A calculating machine according to claim 2, wherein the stages of the multistage display device include number tube circuits, the anodes of the number tubes are connected in sequence to a source of electric potential under the control of the outputs of the timer circuit at a frequency such that numbers appear steady by the persistence effect of ocular vision, a circuit connecting the cathodes of the number tubes shaped to the same digit together as groups of cathodes; and wherein the calculating machine further includes a buffer counter having 10 count state outputs including a 0 count state output; a group of four bistable circuits and whose inputs are connected to the outputs of the count state and whose outputs are connected to the groups of cathodes so that the 10 count states are connected to correspond with the groups of cathodes shaped to the digit corresponding to the count stAte respectively; and a third set of AND gates and accompanying circuit connecting at least one input of a gate of the third set of gates to enter a train of pulses equal in number to the number of the digit in the shift register buffer into the buffer when one of the outputs of the timer circuit is energized.
Claim 5
Dependent Claim
97 words
A calculating machine according to claim 2 including circuit means causing during one cycle of the timer circuit the number of shift pulses transmitted to the number store register to be one less than the number of stages so that the decimal point and the number move one stage to the right, and causing this to be repeated for each cycle of the timer circuit until either the decimal point count reaches zero or until at the next higher stage after the predetermined stage a nonzero digit is presented in the predetermined stage of the visual display.
Claim 6
Dependent Claim
117 words
A calculating machine according to claim 1, wherein a stage of the number store register is internally interconnected as a decade counter to form a shift register buffer; and wherein the calculating machine further includes a carry store whose input is connected to an output of the shift register buffer, and a circuit including a second set of AND gates connected to control the passage of a train of 10 pulses from the input decade counter into the shift register buffer to circulate the digit stored in the counter so that when the digit passes through the zero digit valve a pulse is emitted from the decade counter to energize a carry output of the carry store.
Claim 7
Dependent Claim
76 words
A calculating machine according to claim 1 including sensing means having an input from the output of the timer circuit which corresponds to a stage on the visual register one stage higher than the predetermined stage in the visual display for the highest significant digit of the number entered in the number store register and means responsive to said sensing means to shift the position of the highest significant digit one stage down the display device.
Claim 8
Dependent Claim
215 words
A calculating machine according to claim 6, wherein the display device includes 10 neon bulbs to represent the position of the decimal point in the number displayed on the visual display, means connecting one conductor of each of the neon bulbs to an output of the timer circuit, means connecting the other conductor of each neon bulb in in ascending order of a 10 count state respectively, means providing a 10 count state with the zero count state corresponding to the decimal point at the highest significant digit end of the visual display, and a decimal point decade counter having an output which is energized when the decimal point count is zero, and a further set of AND gates and corresponding circuit means connecting the latter AND gate outputs to the input of the decimal point counter, connecting one input of at least some of these gates to the output of the timer circuit which corresponds to a stage on the visual register one stage higher than the predetermined stage in the visual display for the highest significant digit of the number entered in the number store register, and connecting at least one input of one of these gates to the output of the timer circuit which is connected to the decimal point neon bulbs.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-01-31 | 1975-08-02 | 1976-02-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-01-31 | 1979-08-02 | 1980-02-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-01-31 | 1983-08-02 | 1984-02-01 | $7700.00 | Window Closed / Lapsed |