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Patent US5047360A successfully refreshed from Google Patents.
US5047360A
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Method of manufacture thin film transistors
Assignee: US Philips Corp
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Filing: 1989-08-08
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Granted: 1991-09-10
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Expires: 2009-08-08
Abstract
Abstract A TFT is fabricated by providing on a substrate (10), and over a gate (12), a sequentially formed multi-layer structure consisting of a gate insulator layer (14), an intrinsic semiconductor, e.g. a-Si or polysilicon, layer (16) for the channel, a doped semiconductor, e.g. n type a-Si or polysilicon, layer (18) for source and drain contact regions and a passivating layer (20). The layer (18) extends completely over and covers the channel region of the layer (16). Thereafter, the portion (30) of layer (18) overlying the channel region is converted by a compensating doping implant to a highly resistive form separating the source and drain contact regions, and windows (22, 24) are defined in the passivating layer (20) into which source and drain contacts (26, 28) are deposited. In this way critical interfaces are protected from contamination. The TFT is suitable for use as a switching element in active matrix display devices, e.g. LC-TVs.
Inventors
- 👤 Keith H. Nicholas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 09:40
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0316; H10D10/00; H10D10/01; G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/136; G02F1/1362; G02F1/1368; H10D30/0321; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/6732; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6746; G02F2202/00; G02F2202/10; G02F2202/103; G02F2202/104; Y; Y10; Y10S; Y10S148/00; Y10S148/018; Y10S148/105; Y10S438/00; Y10S438/914; Y10S438/919
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
158 words
A method of fabricating a TFT comprising the steps of (a) forming a gate electrode on a substrate; (b) forming a multi-layer structure over said gate electrode on said substrate, said multi-layer structure including in superimposed relationship: a gate insulator layer, an intrinsic semiconductor layer providing a channel region, a doped semiconductor layer extending over said channel region, and a passivating layer; (c) forming windows in said passivating layer to expose respective underlying areas of said doped semiconductor layer, said windows being above said doped semiconductor layer at respective sides of said gate electrode; (d) depositing contact material into said windows to form source and drain contacts, and (e) implanting further dopants into said doped semiconductor layer through said passivating material by using said contact material in said windows as a mask, said further dopants converting said doped semiconductor layer between said contact material into a high resistance region, said high resistance region being above said gate electrode.
Claim 2
Independent Claim
158 words
A method of fabricating a TFT comprising the steps of (a) forming a gate electrode on a substrate; (b) forming a multi-layer structure over said gate electrode on said substrate, said multi-layer structure including in superimposed relationship: a gate insulator layer, an intrinsic semiconductor layer providing a channel region, a doped semiconductor layer extending over said channel region, and a passivating layer; (c) forming windows in said passivating layer to expose respective underlying areas of said doped semiconductor layer, said windows being above said doped semiconductor layer at respective sides of said gate electrode; (d) depositing contact material into said windows to form source and drain contacts, and (e) implanting further dopants into said doped semiconductor layer through said passivating material by using said contact material in said windows as a mask, said further dopants converting said doped semiconductor layer between said contact material into a high resistance region, said high resistance region being above said gate electrode.
Claim 3
Dependent Claim
24 words
A method according to claim 1, wherein said intrinsic semiconductor layer and said doped semiconductor layer are formed in step (b) of amorphous silicon.
Claim 4
Dependent Claim
23 words
A method according to claim 1, wherein said intrinsic semiconductor layer and said doped semiconductor layer are formed in step (b) of polysilicon.
Claim 5
Dependent Claim
27 words
A method according to claim 1, wherein step (b) is carried out by sequentially depositing said intrinsic semiconductor layer and said doped semiconductor layer as separate layers.
Claim 6
Dependent Claim
26 words
A method according to claim 1, wherein step (b) is carried out by doping a thickness of said intrinsic semiconductor layer to form said doped semiconductor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1994-09-09 | 1995-03-11 | 1995-09-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-09-09 | 1999-03-11 | 1999-09-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-09-09 | 2003-03-11 | 2003-09-10 | $7700.00 | Window Closed / Lapsed |