← Back to Patent Explorer
US4882295A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of making a double injection field effect transistor

Assignee: Energy Conversion Devices Inc
•
Filing: 1989-03-27
•
Granted: 1989-11-21
•
Expires: 2009-03-27
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract Double injection field effect transistors, which may be horizontally or vertically arranged, each include a body of semiconductor material extending between two current-carrying electrodes and forming a current path therebetween. The semiconductor body of each may be substantially intrinsic or lightly doped. One or more control electrodes or gates located adjacent to each current path project a variable electric field over the ambipolar path, which modulates current by controlling the amount of charge carriers of both polarities injected into the semiconductor body. In most of the single gate embodiments, the electrodes extend across a portion, preferably a major portion such as 75% or 90%, or the length of the current path, but not the entire length of the current path. The embodiments having a plurality of gates typically have two insulated gates, one extending from the anode electrode and the other extending from the cathode electrode. The gates in a single device may overlap. Embodiments having electrodes with doped microcrystalline regions for improved carrier injection are disclosed. Methods for making planar double injection field effect transistors having a plurality of deposited noncrystalline semiconductor layers for clean interface formation between semiconductor layers are also disclosed.

Inventors

  • 👤 Wolodymyr Czubatyj
  • 👤 Michael G. Hack
  • 👤 Michael Shur

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 13:31
CPC Classifications
H; H10; H10H; H10H20/00; H10H20/80; H10H20/81; H10H20/817; H10H20/818; H01; H01S; H01S5/00; H01S5/04; H01S5/042; H01S5/0421; H01S5/0422; H01S5/30; H10D; H10D12/00; H10D30/00; H10D30/202; H10D30/80; H10D30/87; H10D30/871; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859; H10H20/062; H01S5/06; H01S5/062; H01S5/06203; Y; Y10; Y10S; Y10S148/00; Y10S148/105

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 115 words
A method of forming a thin film electronic device comprising the steps of: forming a conductive gate on an insulating substrate; forming an insulating layer over said gate; depositing a layer of substantially intrinsic noncrystalline semiconductor material over said insulating layer; forming a layer of etchable metal over said noncrystalline layer and patterning said metal, said metal being etchable by an etchant which does not readily adversely affect the electronic properties of said layer during etching; depositing a first layer of doped noncrystalline semiconductor material over said patterned metal layer; removing said metal layer by etching, and at the same time, removing that portion of said first doped layer which overlies said etchable metal layer.
Claim 2
Independent Claim 115 words
A method of forming a thin film electronic device comprising the steps of: forming a conductive gate on an insulating substrate; forming an insulating layer over said gate; depositing a layer of substantially intrinsic noncrystalline semiconductor material over said insulating layer; forming a layer of etchable metal over said noncrystalline layer and patterning said metal, said metal being etchable by an etchant which does not readily adversely affect the electronic properties of said layer during etching; depositing a first layer of doped noncrystalline semiconductor material over said patterned metal layer; removing said metal layer by etching, and at the same time, removing that portion of said first doped layer which overlies said etchable metal layer.
Claim 3
Dependent Claim 23 words
A method as defined in claim 1 further comprising the step of: depositing a second doped layer after removing said etchable metal layer.

References Cited (Backward Citations)

US3333115A Cited
US3544864A Cited
US4605941A Cited
US4425572A Cited
US4458261A Cited
EP0090661A2 Cited
JPS60183770A Cited
US4797108A Cited
US4720736A Cited
US4646424A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-11-20 1993-05-22 1993-11-21 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-11-20 1997-05-22 1997-11-21 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-11-20 2001-05-22 2001-11-21 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag