Patent US5047355A successfully refreshed from Google Patents.
US5047355A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor diode and method for making it
Assignee: Mosaid Technologies Inc
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Filing: 1989-09-12
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Granted: 1991-09-10
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Expires: 2009-09-12
Abstract
Abstract A semiconductor diode has three adjacent regions. The doped regions are doped in the same manner and are separated from one another by a third, intrinsic region. The intrinsic region is dimensioned such that upon application of a specific external voltage at the operating temperature of the diode, it is possible for charge carriers to tunnel from one doped region to the other doped region through the intrinsic region. The semiconductor diode has a planar structure on a semiconductor substrate. A semconductor diode of this kind is suitable for use as a protective diode for other components, particularly when they are mounted on substrates consisting fo connecting semiconductors.
Inventors
- 👤 Jakob Huber
- 👤 Ewald Pettenpaul
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 07:05
CPC Classifications
H; H10; H10D; H10D8/00; H10D8/50; Y; Y10; Y10S; Y10S438/00; Y10S438/979
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
114 words
In a process for making a protective device in a semiconductor substrate having at least a semi-insulating surface region for protecting at least one semiconductor device located in the substrate and subject to potentially harmful voltages, the process comprising the steps of: epitaxially applying a doped semiconductor layer on the entire surface region; structuring the semiconductor layer photolithographically to form two doped regions separated by a third region wherein the semiconductor layer is fully removed to expose the semi-insulating surface in the third region; depositing ohmic contacts on the two regions; alloying the ohmic contacts; passivating the surface region; and connecting the ohmic contacts to the one semiconductor device for dissipating the harmful voltages.
Claim 2
Dependent Claim
114 words
In a process for making a protective device in a semiconductor substrate having at least a semi-insulating surface region for protecting at least one semiconductor device located in the substrate and subject to potentially harmful voltages, the process comprising the steps of: epitaxially applying a doped semiconductor layer on the entire surface region; structuring the semiconductor layer photolithographically to form two doped regions separated by a third region wherein the semiconductor layer is fully removed to expose the semi-insulating surface in the third region; depositing ohmic contacts on the two regions; alloying the ohmic contacts; passivating the surface region; and connecting the ohmic contacts to the one semiconductor device for dissipating the harmful voltages.
Claim 3
Dependent Claim
99 words
In a process for making a protective device in a semiconductor substrate having at least a semi-insulating surface region for protecting at least one semiconductor device located in the substrate and subject to potentially harmful voltages, the process comprising the steps of: forming a doped semiconductor layer to cover the semi-insulating surface region completely; forming an intrinsic conductivity region between two regions of the doped semiconductor layer by insulation-implanatation. depositing ohmic contacts on the two regions; alloying the ohmic contacts; passivating the surface region; and connecting the ohmic contacts to the one semiconductor device for dissipating the harmful voltages.
Claim 4
Dependent Claim
99 words
In a process for making a protective device in a semiconductor substrate having at least a semi-insulating surface region for protecting at least one semiconductor device located in the substrate and subject to potentially harmful voltages, the process comprising the steps of: forming a doped semiconductor layer to cover the semi-insulating surface region completely; forming an intrinsic conductivity region between two regions of the doped semiconductor layer by insulation-implanatation. depositing ohmic contacts on the two regions; alloying the ohmic contacts; passivating the surface region; and connecting the ohmic contacts to the one semiconductor device for dissipating the harmful voltages.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-09-09 | 1995-03-11 | 1995-09-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-09-09 | 1999-03-11 | 1999-09-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-09-09 | 2003-03-11 | 2003-09-10 | $7700.00 | Window Closed / Lapsed |