US4468851A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for making a heterojunction source-drain insulated gate field-effect transistors utilizing diffusion to form the lattice
Assignee: United States Department of the Navy
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Filing: 1981-12-14
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Granted: 1984-09-04
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Expires: 2001-12-14
Abstract
Abstract An apparatus for and a method of making heterojunction source-drain insulated gate field-effect transistors in order to obtain higher gain-bandwidth products at microwave frequencies. A semi-insulating InP semiconductor substrate is provided with a ternary alloy layer of p-type Ga 0 .47 In 0 .53 As, or optionally, an acceptor-doped p-type bulk of Ga 0 .47 In 0 .53 As can be substituted. Troughs are shaped in the substrate and layer for receiving a material lattice-matched to the n + p-type Ga 0 .47 In 0 .53 As to perform as the source and drain contacts, n + doped InP might be a suitable material. An optional method for forming the contacts calls for directing a stream of phosphine and hydrogen onto source and drain contact windows contacting the Ga 0 .47 In 0 .53 As which is heated to 750° C. for about 15 minutes. This creates graded heterojunction source and drain contacts having a lattice-matching variable composition.
Inventors
- 👤 Herman H. Wieder
- 👤 Arthur R. Clawson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 01:08
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D30/00; H10D30/60; H10D62/80; H10D62/82; H10D62/824; H10D62/85; H10D62/852; Y; Y10; Y10S; Y10S148/00; Y10S148/05; Y10S148/053; Y10S148/067; Y10S148/084; Y10S438/00; Y10S438/936
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
181 words
A method of making an inversion mode metal-insulator-semiconductor field-effect transistor having heterojunction source and drain contact junctions comprising: providing a semi-insulating InP semiconductor substrate; growing a ternary alloy layer of p-type Ga 0 .47 In 0 .53 As epitaxially on a portion of the semi-insulating InP semiconductor substrate; coating the exposed semi-insulating semiconductor substrate and the ternary alloy layer with a dielectric; opening source and drain contact windows through the dielectric coating and in contact with the ternary alloy layer; exposing the open source and drain contact windows to a stream of phosphine and hydrogen while heating the p-type Ga 0 .47 In 0 .53 As to about 750° C. for about 15 minutes to create a chemical reaction at the surface of the p-type Ga 0 .47 In 0 .53 As producing a graded index heterojunction composed of InP through In x Ga 1-x As y P 1-y to Ga 0 .47 In 0 .53 As; and superposing a metal gate electrode on the dielectric coated ternary alloy layer in a region lying between the heterojunction source and drain contacts.
Claim 2
Independent Claim
181 words
A method of making an inversion mode metal-insulator-semiconductor field-effect transistor having heterojunction source and drain contact junctions comprising: providing a semi-insulating InP semiconductor substrate; growing a ternary alloy layer of p-type Ga 0 .47 In 0 .53 As epitaxially on a portion of the semi-insulating InP semiconductor substrate; coating the exposed semi-insulating semiconductor substrate and the ternary alloy layer with a dielectric; opening source and drain contact windows through the dielectric coating and in contact with the ternary alloy layer; exposing the open source and drain contact windows to a stream of phosphine and hydrogen while heating the p-type Ga 0 .47 In 0 .53 As to about 750° C. for about 15 minutes to create a chemical reaction at the surface of the p-type Ga 0 .47 In 0 .53 As producing a graded index heterojunction composed of InP through In x Ga 1-x As y P 1-y to Ga 0 .47 In 0 .53 As; and superposing a metal gate electrode on the dielectric coated ternary alloy layer in a region lying between the heterojunction source and drain contacts.
Claim 3
Dependent Claim
47 words
A method according to claim 1 in which the steps of providing a semi-insulating InP semiconductor substrate and the growing of a ternary alloy layer are eliminated and in place of the layered structure an acceptor-doped p-type bulk Ga 0 .47 In 0 .53 As is utilized.
Claim 4
Dependent Claim
20 words
A method according to claim 2 in which the step of opening includes a sputter etching of the dielectric layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-09-04 | 1988-03-05 | 1988-09-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-09-04 | 1992-03-05 | 1992-09-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-09-04 | 1996-03-05 | 1996-09-04 | $7700.00 | Window Closed / Lapsed |