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US5037782A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of making a semiconductor device including via holes

Assignee: Mitsubishi Electric Corp
•
Filing: 1989-07-06
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Granted: 1991-08-06
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Expires: 2009-07-06
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Abstract

Abstract A semiconductor substrate having first and second opposing surfaces is provided with a plurality of semiconductor elements having their electrodes arranged on the first surface. A plurality of small recesses are first formed in the second surface at locations opposite selected ones of the electrodes of the semiconductor elements. After the formation of the small recesses, the material of the substrate in and around the small recesses is etched away so that a larger recess encompassing the small recesses is formed and, at the same time, the small recesses are caused to extend through the substrate to thereby form through-holes which extend from the larger recess to the selected ones of the electrodes.

Inventors

  • 👤 Taeko Nakamura
  • 👤 Yutaka Yoshii

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-04 19:05
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/021; H10W20/023; H10W20/0234; H10W20/0242; H10W20/20; H10W20/211; H10W20/212; H10W20/2125; Y; Y10; Y10S; Y10S148/00; Y10S148/135

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 168 words
A method of making a semiconductor device comprising: forming a plurality of semiconductor elements in a semiconductor substrate at a first surface of said substrate; forming electrodes contacting said semiconductor elements on said first surface of said semiconductor substrate; forming a plurality of relatively small recesses by etching a second surface of said substrate opposite said first surface at locations opposite selected ones of said electrodes; removing by etching the material of said substrate in and around said small recesses to form a single, relatively large recess encompassing said small recesses including a third surface intermediate said first and second surfaces and, at the same time, further etching in said plurality of small recesses to extend the small recesses through said substrate to form through-holes which extend from said third surface in said large recess to said selected ones of said electrodes; and coating said larger recess, the inner surfaces of said through-holes, and said second and third surfaces of said semiconductor substrate with a continuous metallic layer.
Claim 2
Independent Claim 168 words
A method of making a semiconductor device comprising: forming a plurality of semiconductor elements in a semiconductor substrate at a first surface of said substrate; forming electrodes contacting said semiconductor elements on said first surface of said semiconductor substrate; forming a plurality of relatively small recesses by etching a second surface of said substrate opposite said first surface at locations opposite selected ones of said electrodes; removing by etching the material of said substrate in and around said small recesses to form a single, relatively large recess encompassing said small recesses including a third surface intermediate said first and second surfaces and, at the same time, further etching in said plurality of small recesses to extend the small recesses through said substrate to form through-holes which extend from said third surface in said large recess to said selected ones of said electrodes; and coating said larger recess, the inner surfaces of said through-holes, and said second and third surfaces of said semiconductor substrate with a continuous metallic layer.
Claim 3
Dependent Claim 25 words
The method according to claim 1 including forming said continuous metallic layer by plating so that said continuous metallic layer is a plated heat sink.
Claim 4
Independent Claim 166 words
A method of making a semiconductor device comprising: forming a plurality of semiconductor elements in a semiconductor substrate at a first surface of said substrate; forming electrodes contacting said semiconductor elements on said first surface of said semiconductor substrate; forming a plurality of relatively small recesses in a second surface of said substrate opposite said first surface at locations opposite selected ones of said electrodes; removing the material of said substrate in and around said small recesses to form a single, relatively large recess encompassing said small recesses including a third surface intermediate said first and second surfaces and, at the same time, further removing material in said plurality of small recesses to extend the small recesses through said substrate to form through-holes which extend from said third surface in said large recess to said selected ones of said electrodes; and coating said large recess, the inner surfaces of said through-holes, and said second and third surfaces of said semiconductor substrate with a continuous metallic layer.
Claim 5
Independent Claim 166 words
A method of making a semiconductor device comprising: forming a plurality of semiconductor elements in a semiconductor substrate at a first surface of said substrate; forming electrodes contacting said semiconductor elements on said first surface of said semiconductor substrate; forming a plurality of relatively small recesses in a second surface of said substrate opposite said first surface at locations opposite selected ones of said electrodes; removing the material of said substrate in and around said small recesses to form a single, relatively large recess encompassing said small recesses including a third surface intermediate said first and second surfaces and, at the same time, further removing material in said plurality of small recesses to extend the small recesses through said substrate to form through-holes which extend from said third surface in said large recess to said selected ones of said electrodes; and coating said large recess, the inner surfaces of said through-holes, and said second and third surfaces of said semiconductor substrate with a continuous metallic layer.
Claim 6
Dependent Claim 25 words
The method according to claim 5 including forming said continuous metallic layer by plating so that said continuous metallic layer is a plated heat sink.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1994-08-05 1995-02-04 1995-08-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1998-08-05 1999-02-04 1999-08-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2002-08-05 2003-02-04 2003-08-06 $7700.00 Window Closed / Lapsed

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