US5031010A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device and method of manufacturing the same
Assignee: Toshiba Corp
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Filing: 1990-12-03
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Granted: 1991-07-09
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Expires: 2010-12-03
Abstract
Abstract In a semiconductor memory device having a floating gate structure, the floating gate electrode is composed of 2 to 10 silicon grains. With the floating gate electrode, the insulation film, formed on the floating gate electrode, can have a high breakdown voltage. In a method of manufacturing a semiconductor memory device having a floating gate structure, an insulation film is formed on the silicon substrate, portions of the insulation film which are on the drain and source forming regions of the silicon substrate are removed, and a silicon layer is formed on the silicon substrate by an epitaxial growth process, constituting a floating gate, composed of 2 to 10 silicon grains. According to the manufacturing method, the insulation film formed on the floating gate electrode can have a high breakdown voltage.
Inventors
- 👤 Yuuichi Mikata
- 👤 Toshiro Usami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 18:50
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685; H10D64/00; H10D64/01; H10D64/031; H10D64/035
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
52 words
A nonvolatile semiconductor memory device with a floating gate structure, comprising: a silicon substrate; a floating gate electrode composed of 2 to 10 silicon grains for limiting a number of asperities therein, said floating gate electrode having a potential; and a control electrode for controlling the potential of said floating gate electrode.
Claim 2
Dependent Claim
52 words
A nonvolatile semiconductor memory device with a floating gate structure, comprising: a silicon substrate; a floating gate electrode composed of 2 to 10 silicon grains for limiting a number of asperities therein, said floating gate electrode having a potential; and a control electrode for controlling the potential of said floating gate electrode.
Claim 3
Dependent Claim
130 words
A nonvolatile semiconductor memory device having a floating gate structure, comprising: a silicon substrate having a drain region and a source region; a floating gate electrode composed of 2 to 10 polysilicon grains for limiting a number of asperities therein, said floating gate electrode having a potential; a first insulation film formed on said floating gate electrode; a control gate electrode comprising a polysilicon layer formed on said first insulation film, for controlling the potential of said floating gate electrode; a second insulation film formed on the structure, and having contact holes leading to at least one of said drain region and source region; and electrode layers extending in said contact holes formed in said second insulation film, and contacting at least one of said drain region and source region.
Claim 4
Dependent Claim
130 words
A nonvolatile semiconductor memory device having a floating gate structure, comprising: a silicon substrate having a drain region and a source region; a floating gate electrode composed of 2 to 10 polysilicon grains for limiting a number of asperities therein, said floating gate electrode having a potential; a first insulation film formed on said floating gate electrode; a control gate electrode comprising a polysilicon layer formed on said first insulation film, for controlling the potential of said floating gate electrode; a second insulation film formed on the structure, and having contact holes leading to at least one of said drain region and source region; and electrode layers extending in said contact holes formed in said second insulation film, and contacting at least one of said drain region and source region.
Claim 5
Dependent Claim
152 words
A nonvolatile semiconductor memory device with a floating gate structure, comprising: a silicon substrate having a drain region and a source region formed therein; a first polysilicon layer a having floating gate electrode composed of 2 to 10 polysilicon grains for limiting a number of asperities therein, said floating gate electrode having a potential; second polysilicon layers formed on at least one of said drain region and source region; a first insulation film formed on said floating gate electrode; a third polysilicon layer formed on said first insulation film, forming a control gate electrode for controlling the potential of said floating gate electrode; fourth polysilicon layers formed on said second polysilicon layers; a second insulation film formed on the structure, and having contact holes formed therein leading to said fourth polysilicon layers; and electrode layers extending in said contact holes formed in said second insulation film, and contacting said second polysilicon layers.
Claim 6
Dependent Claim
152 words
A nonvolatile semiconductor memory device with a floating gate structure, comprising: a silicon substrate having a drain region and a source region formed therein; a first polysilicon layer a having floating gate electrode composed of 2 to 10 polysilicon grains for limiting a number of asperities therein, said floating gate electrode having a potential; second polysilicon layers formed on at least one of said drain region and source region; a first insulation film formed on said floating gate electrode; a third polysilicon layer formed on said first insulation film, forming a control gate electrode for controlling the potential of said floating gate electrode; fourth polysilicon layers formed on said second polysilicon layers; a second insulation film formed on the structure, and having contact holes formed therein leading to said fourth polysilicon layers; and electrode layers extending in said contact holes formed in said second insulation film, and contacting said second polysilicon layers.
Claim 7
Dependent Claim
78 words
A semiconductor memory device according to claim 3, wherein said fourth polysilicon layers comprise contact holes formed therein and continuous to said contact holes formed in said second insulation film, and wherein said semiconductor memory device further comprises third insulation films formed between said second polysilicon layers and said fourth polysilicon layers, said third insulation films having contact holes formed therein and continuous to said contact holes formed in said fourth polysilicon layers and said second insulation film.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-08 | 1995-01-07 | 1995-07-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-08 | 1999-01-07 | 1999-07-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-08 | 2003-01-07 | 2003-07-09 | $7700.00 | Window Closed / Lapsed |